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Synchronizing Dad’s Antique Impulse Clocks using LabVIEW FPGA

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Synchronizing Dad’s Antique Impulse Clocks using LabVIEW FPGA

A Dabbling in Building Automation

In 1972, the University of Tennessee, Knoxville updated their campus clock system to a new Simplex brand sweep-second-hand synchronized system. A student at the time, my dad, Rick Kuhlman Jr., discovered that the old 24-volt DC impulse slave clocks were going up for silent auction. With his dad’s help (my grandfather F.B. Kuhlman Sr.), he put in a max bid of 88 dollars. As a sort of clock enthusiast, he was hoping to get at least a few of the truly antique clocks produced as early as 1919 by IBM (believe it or not). To his surprise, UT (the real UT of course – University of Tennessee) contacted him to tell him that he had won the bid. Little did he know, he had actually purchased a whole closet full of impulse clocks of differing brands and time periods ranging from 1919 up the 1960s. He counted it a lucky day as he needed two trips with a station wagon to get all the new/old clocks home. Literally, over the next 38 years every place around him needed a synchronized clock system. First, he outfitted his parents house 1973-present, his fraternity house room 1972-1974, his dad’s beer-distributor warehouse and offices from 72-78, and his own home from 1980-present. At one point, he tried to make a clock donation to our church during renovations, but they turned him down.

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Figure 1 – <left picture>My dad (right) and his brother (left) show off one of the new clocks. <right picture>My dad and his college roommate, March of 73. He already has a clock installed in his Pike house dorm room.

In 2008, he was appointed the leader of a downtown Knoxville community effort called the Knoxville Fellows Program, a restaurant, and a live music theater. The overseeing non-profit was renovating two connected buildings comprising of over 30,000 square feet on Market Square for this purpose. Amongst all of his other important responsibilities in this project he made it a priority that the electrical crew ran three clock wires to every major room in the property including offices, apartments, the kitchen, backstage, and wherever else.

He had enough clocks for the job, the building is wired, but the final thing about my dad’s antique impulse clocks (besides being almost 100 years old in some cases) is that they are slave clocks. They themselves do not have a concept of time. They are disciplined and synchronized by pulses from a master clock. In my dad’s previous installations the master clock was as simple as a 1 RPM motor nudging a switch every minute or as legit as a real antique master clock designed specifically for the job. My dad’s 2008 Fathers Day present was a custom master clock hand-built by his son (that’s me) and written in LabVIEW FPGA (that’s my favorite NI product). The rest of this article will cover my spare-time process to that end.

Simplex/IBM 59th minute 3-Wire Clock

This first foray into created a master clock controller was scoped to a particular type of clock mechanism. Out of the many protocols used for synchronization over the years, my dad had enough Simplex/IBM 59th minute 3-wire clocks for our project

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Figure 2: The Simplex/IBM 59th minute 3-wire protocol hookup wires

This type of clock advances one minute every time it receives a 24V pulse on the normal impulse input. Using a mechanical switching mechanism, it will stop responding to pulses on the normal line at the 59th minute of any given hour. The clock must then receive a 24V pulse on the “59th minute” line to advance to the next hour. This mechanism allows the whole system outfitted with multiple slave clocks to synch up with the master at the top of every hour.

Here is how it works: Failure modes and synchronization theory

  1. A slave clock is ahead of real time, because it accidentally advances multiple minutes from one pulse during an hour. It will synch, because the minute hand will get stuck at the 59th minute until the master catches up.
  2. A slave lags real time, because it fails to advance a minute from any number of pulses during the hour. It will synch because the master clock sends a sequence of 20 catch-up pulses to advance slow clocks to the 59th minute before asserting the “59th minute” line to send all clocks to the next hour.
  3. A slave lags between 20 and 50 minutes behind real time, because there is a temporary issue in the electromechanical mechanism, it has been manually set, or has lost connection for some amount of time. Because there are only 20 catch up pulses at the 59th minute, a clock more than 20 minutes behind requires a special consideration. It will synch, because the first 30 minutes of each hour the master pulses both lines to drag the minute hand along until till next set of catch up pulses. Without this feature the minute hand would get stuck in the previous hour at the 59th minute and subsequently be exactly an hour slow from then on.
  4. Other more severe or consistent failure modes of more than 30 minutes in either direction indicate an issue in the slave clock that requires fixing or replacement.

To illustrate my implementation, lets go through a timing diagram I used for a complete hour.

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Figure 3: The Simplex/IBM 59th minute 3-wire protocol timing diagram with zoomed views of the 1st and 59th minute

In the first 30 minutes both lines pulse high during the last three seconds of each minute. This advances any clock one minute forward during this time. The second 30 minutes only the normal line pulses. This advances all clocks, unless they are held at the 59th minute for synchronization. In the last minute of the hour, the normal line pulses every few seconds issuing catchup pulses to pull any slow clocks up to the 59th minute. Finally, in the last 3 second of the hour, both line go high to take all clocks (synchronized at this point) into the next hour.

Hardware Setup

The system is based on the Spartan 3E Starter Board, a Xillinx FPGA evaluation board. This board is ported for use with LabVIEW FPGA in academia. You can get the driver here:

Using this hardware for my hobby project was nice because of the built-in supported features. I used output digital lines to activate the relays, 2 buttons to set the master clock time, a button to advance the clock system manually, and the LCD to display the master time and a little message for my dad: “Dad’s Clocks.”

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Figure 4: The Spartan 3E board with labels on the parts used for this project

Overall, the system uses this board as the brain and master timebase. TTL-controlled relays feed the 24V impulse signals to the network of daisy chained slave clocks. The LCD output shows the current master time.

System Components

  • Spartan 3E Starter Board
  • ER-4 Relay Module
  • Enclosure
  • Wiring and Connectors

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Figure 5: Hardware Setup: A few digital outputs from the Spartan Board control the relays to click the lines of the clock.

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Figure 6: Inside the actual enclosure: Spartan board mounted and wired to the relay board

LabVIEW FPGA Programming

The Spartan boards allows the user to create and debug you LabVIEW FPGA program using the USB programming port. However, there is some on-board flash that can store you program and load it to the FPGA at startup. This mechanism allows for the deployment of the LabVIEW FPGA VI to the board such that it “boots up” into the clock program when powered on. Lets take a deeper look at the LabVIEW FPGA program used for this application.

Main Clock Loop

The main clock-keeping loop is very simple. Essentially, it is a series of counters. The onboard oscillator of the board is 50Mhz, therefore the first counter measures seconds by counting every 50 million ticks on that clock. This is the origin of the tagline “How to Count to 50 Million 86400 Times a Day”, where 86400 is the number of seconds in a day. Once you have seconds making a 60 counter on that for minutes and a 60 counter on that for hours is trivial.

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Figure 7: This while loop executes on each tick of a one-second counter. The counters in this loop keep track of the second, minutes, and hours.

The clock is set like an old school alarm clock with two buttons: fast and slow. The fast button makes the loop in figure 6 execute at .5ms instead of the normal second, making it easy to run through 24 hours quickly. The slow button changes the timebase to 10ms so that you can hone down to a particular minute easily.

Pulses Loop

The pulse loop is just a set of cases that execute each of the different operating modes of the timing diagram:

  • 0-30 minutes where both relay are working
  • 31-58 minutes where only the normal line is working
  • 59th minute catchup pulses on the normal line

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Figure 8: Main Case structure Defining the operating modes. Case Shown is the 0-30 minutes case where both relays work every minute.

LCD Controller Loop(s)

There are two loops used to output the current time and my special message to my dad on the LCD screen. The first loop converts the hours, minutes, and seconds to the corresponding ASCII bytes. The algorithm breaks out each individual digit of the time and adds the magic number 48 to index the number into the correct characters in the standard ASCII table.

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Figure 9: Conversion from hours, minutes, and seconds to ASCII bytes into an array.

For the second loop, there is an example already written and included with the Spartan board driver for writing bytes to the LCD screen. Using this simple example, the loop writes the “time” array of bytes and my message to the LCD screen continuously.

The Final Product

With the Xilinx Spartan 3E Starter Kit, some external hardware, and a fairly simple LabVIEW FPGA program, I have created a master clock for my dad’s antique impulse slave clock. We are currently using this master to control and synchronize 15 clocks spread through a 30,000 square-foot building. Since all of the wiring was done beforehand we were able to install this crafty master in one of the control rooms.

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Figure 10: I placed the master clock controller in the one of the control rooms for the building.

This project was not only a successful system but a successful Father’s Day gift. He is so happy to see the clocks clicking along “like clockwork.” Reviving his antique clocks from their basement dwelling was certainly one of the best gifts I could have given. However, as you can see from this document and the fun that I had doing it with him, it was my pleasure.

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Figure 11: Clocks hung around the buildling

NI Employee (retired)

Very impressive    


sounds like fun alright.  Now if only the clocks in your pics were displaying the same time


Those clocks are beautiful. I can only imagine this was a very fun project.