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This IP implements inline, real-time DSP in LabVIEW FPGA to apply arbitrary channel models to RF data. Fading profiles are computed in real-time on the host, and dowloaded to the FPGA where they are interpolated and applied to the data stream.
This IP uses an FPGA-based control loop to rapidly adjust device output power to reach a desired input power, when an load or amplifier of unknown gain is connected between the output and input.