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myPWM_Decoder

Description:

This project was created to measure the duty cycle and period of PWM signals. Therefore it counts the HIGH-time and LOW-time on the FPGA and stores the values on the front panel.

The RT VI RT_PWM-Decoder.vi calls the myRIO_PWM_Decoder.vi on the FPGA, takes the measured times and sums them up to get the period in seconds and calculates the duty cycle in percentage.

myRIO_PWM_Decoder.vi calls PWM_CTR.vi  which measures HIGH and LOW-times by detecting the corresponding edges in the signal. It is used on each of the PWM Decoder Input Pins.

Instructions on how to use Code: 

If you do not have the NI LabVIEW FPGA module you can still run this code by pointing the Open FPGA Reference to the bitfile (lvbitx) attached at the bottom of this document.

For more details on this:

How Do I Download a Bitfile to My Target Without LabVIEW FPGA?

Opening a Reference to an FPGA VI, Build Specifcation, or Bitfile (FPGA Interface)

1. Connect your sensor to the NI myRIO

2. Compile myRIO_PWM_Decoder.vi on FPGA Target using the local compile farm if you downloaded Xilinx Compile Tools or a compile server or cloud

3. You can use the bitfile instead of compiling the FPGA VI if you wish to run the code as is

4. Run RT_PWM-Decoder.vi and measure duty cycle and period

Modified Pin-out:

Connector A DIO7:0 – each pin acts as a PWM Decoder Input Pin

Connector C DIO7:0 – each pin acts as a PWM Decoder Input Pin

Onboard DIO Button0 and LED0, LED 1, LED2 and LED3 remain untouched

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Code: PWM_Decoder.zip attached

Sunaina K.
Product Marketing Manager for CompactRIO & TSN

Making the intangible, tangible
Comments
Member shox
Member

thanks very much really great work.

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