Re: We need to find a solution for the bitfile name scrambling

Hello Altenbach and Fabiola (and anyone else who has this issue),

I am working on a post-copy scripting VI that should resolve these issues.  In your XML document, you should have a field for <CustomVIPath>.  The current myRIO is linked here.  This VI sets the target address of the myRIO if it was provided.  I will add code to update the Open FPGA Reference VI, which should resolve your issues.  You'll have to include the VI with your installer, place on disk it in LabVIEW 2013\ProjectTemplates\Source\myRIO\scripting\myRIOMetaDataObj, and link to it from the XML.

Altenbach, I believe the problem you are seeing only relates to the Build Spec for the FPGA Main bitfile.  That is, if the user were to recompile their FPGA VI, the new bitfile would have the name spacing shown.  Is your screenshot showing the FPGA Main Properties for configuring the build spec, or a different property window?  In the screen shot below, you can see that the FPGA Bitfile in my project, generated from the Create Project view, has the original name.  The FPGA Main Properties window for the Build Spec shows the updated name.  As such, the same PostCopyScripting VI provided for Fabiola should fix your issues as well - linking the Open FPGA reference to the newly copied bitfile.

I will be contacting each of you individually to provide the PostCopyScripting VI.  Anyone else who needs to call this VI should send me a direct message requesting the VI.

Screenshot 2014-06-03 12.07.37.png

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