We need to find a solution for the bitfile name scrambling

As shown here, the actual bitfile name is retained unchanged, but the expected bitfile name (in the FPGA buils spec) gets mangled with the project name that the user choses, requiring a lenghty FPGA recompile. The current solution is to open the FPGA build spec and point it to the bitfile that is already there, but that should not be necessary, and impacts the user experience.

Is there an xml setting to fix that or is there a bug in the project scripter?

Thanks!

https://decibel.ni.com/content/servlet/JiveServlet/downloadImage/2-75200-175840/450-348/bitfileScramble.png


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