Re: FPGA: Avoiding Feedback Node around a synchronous block in SCTL?

Wow... I've never considered that, but it makes total sense. I always thought that registering the outputs of the Xilinx cores did not change the behavior of the signals at the port map (which would require additional "anticipation" when registering the RFD). But if it is truly just a register, then I suppose we can avoid the caching registers shown in my code above. For instance, in the FIR Compiler, does the "Registered Output" checkbox also control RFD behavior?

Screen Shot 2013-03-28 at 12.52.07 PM.png

I generally register outputs to avoid timing issues, but there is no reason I couldn't register the data outputs (but not RFD) with feedforward nodes on the LabVIEW diagram. That would be a whole lot easier than the caching logic.

Thanks for the tip!

Ryan

Ryan Verret
Product Marketing Engineer
Signal Generators
National Instruments
0 Kudos
(2,863 Views)