Re: FPGA: Avoiding Feedback Node around a synchronous block in SCTL?

Just to extend on the previous comments, in general you must treat any data that may be fed upstream as a next-cycle value. The 4-wire protocol used by the streaming blocks in LabVIEW FPGA (e.g. the High-Throughput nodes) exemplify this where the Ready for Input that feeds into upstream nodes carries a value for the next cycle. That way you are able to register each of those values in the owning diagram and meet the dataflow requirements of LabVIEW.

When you are using Xilinx IP, many of the blocks can be configured to output this "next cycle" value instead of the registered synchronous version. If not, then unfortunately you have to do the work to support the extra cycle of latency.

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