Re: FPGA: Avoiding Feedback Node around a synchronous block in SCTL?

I don't think LV knows your IP block is synchronous to a given clock, so I can't imagine it'll let you remove that FN; I was taught that it treats all blocks (VIs, prims, xnodes, etc.) inside an SCTL as combinatorial logic. It seems like NI would have to make a special rule for VHDL generation that ignores the FN, since connecting an input and an output on the same block is a violation of dataflow itself.

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