FPGA: Avoiding Feedback Node around a synchronous block in SCTL?

Hi,

apologize for the trivial question....

It sometimes happens to me  to feed signals back as the boolean in the following diagram.

The figure below is a simplified example: a synchronous counter that, upon arriving at a given threshold,

re-initialize synchronously to a given value (and again and again). Just as an example.

When I draw this feedback wire, LV did authomatically insert a Feedback Node. This would

make perfect sense if the signal were around a combinatorial block; however here the block, a synchronous counter,

has nothing combinatorial, so the additional Feedback Node seems to me useless. Moreover,

in actual situations, it is very uncomfortable to me, as it complicates the timing.

Is there any way to remove it?

Thanks!

Bruno

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