Re: I wish... FPGA Best Practices

Thanks for the context and feedback.  Really helpful.  I have not done many cRIO systems but I understand the (general) challenges faced.


One common principle that we look to apply in our projects is a more pronounced design phase that is outside of the LabVIEW environment.  For this we look to UML diagram templates.


Another is simulating the system but not just literally in the FPGA sense.  This could help one see integration issues up front and in an environment that is easier to troubleshoot.  A few years ago we were working on a cRIO based system where the deployment was overseas and there wasn't a lot of room for back and forth.  The FPGA was very simple but the RT had it's share of complexity.  We made a simulated model in Windows and were able to exercise all known scenarios.  We are applying this (in concept) to PXI based FPGA systems.  Though they are RF and high bandwidth we do this to test the interfaces and low bandwidth logic.  There are modules to help shake out issues where we need to run at higher bandwidths.


Anyway, I think applying design techniques outside of LabVIEW tends to be counter intuitive in the LabVIEW world (myself included).  NI teaches us that "it is easy" and "no coding needed" which even if we ignore these statements may still have it in some level.  The simulations are another aspect which I would say are best practices.


That said I wonder if this 'talk' could be a panel where there are different perspectives with some questions planned (pre-submitted), on the fly, or combination of the two.  I feel like I know quite a bit on the subject but I still see things that keep me humble.


The other general issue is that LabVIEW FPGA has a much smaller and quieter community than LabVIEW.  The reason is understandable but the result is that there are less resources and discussions happening.  I find that with LabVIEW FPGA some projects tend to be more proprietary which leads to less discussions.  The best thing would be decouple the principles from the projects.  This is not easy but it is really the only way a success can be repeated and a failure can be avoided.


I assume you know of the cRIO Developers Guide  Though dated, I am sure it has good stuff in there.  I haven't studied it but I assume what you are looking for goes beyond and maybe some things have changed since it was published.


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LabVIEW FPGA for High Throughput Applications | VI Week 2020
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