Re: FPGA compilation fail with vivado error DRC 23-20

The behavior you're seeing is likely related to a known issue that is actively under investigation. I believe the CLIP generator will incorrectly assume that the derived clock is never ready, causing the design rule check error you're seeing. This can easily be fixed by editing the vhd file created from the CLIP generator. Find the LabVIEW Clock Port section of the VHDL and change the ready signal to '1' instead of '0'. Here's an example:

---------------------------------------------------------------
--LabVIEW Clock Port: ext_clk_pin36
---------------------------------------------------------------
ext_clk_pin36_lvc <= aDio_in(36);
ext_clk_pin36_lvc_ready <= '1';

 

 

Will

National Instruments

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