Re: Switching clocks for SCTL
The code does compile for a 20 to 200 MHz frequency range from an external clock. I see this a possible solution if I'm using an internal clock.
However, if I go with your suggestion then I'd have to replace the 100 and 40 MHz clocks with a single 200MHz one and do some re-routing, I'm not sure after that if I need to be aware of any possible timing issues that could arise.
I've heard about BUFGMUX for clock selection in Xilinx chips, not sure if we have access to that.