Re: Switching clocks for SCTL
The clock source for the SCTL will need to be constant at compile-time. However, there are some options you could try that might give you similar behavior to dynamically choosing the clock.
- Compile two different bitfiles, one with each clocking option, and dynamically choose which to load in your host VI.
- Create 2 SCTLs in your FPGA code that run simultaneously. Include logic in your code that allows you to choose which loop you care about and are getting data from.