Re: Can I use LVDS (in and out) from those banks which is powered from 3.3V?

Hi Jiangliang,

The Zynq IO pins are capable of many more standards than what is exposed in the CLIP generator.  The Xilinx Select IO manual for 7 Series FPGAs details all the IO capabilities and rules for combining IO standards within a single bank. 

7 Series FPGAs SelectIO Resources User Guide

Starting on page 97, you can see the rule details and all the available IO standards. 

Unfortunately, the "LVDS" IO standard (differential signaling at 1.8V VCC) is only available on HP IO banks, which the Zynq 7020 does not include.  According the the Select IO manual, we would need to find an IO standard that allows 1.8V VCC and differential signaling and be compatible with with the HR IO banks.

If you need to import a differential clock on a 1.8V HR IO bank, I would consider evaluating the Differential HSTL or SSTL IO standards.  You need to take a look at the detailed requirements for these standards and ensure your clock meets the voltage levels (DC bias and differential voltage swings) and termination requirements.

For example, look at the following standards:

DIFF_HSTL_I_18

DIFF_HSTL_II_18

DIFF_SSTL18_I

DIFF_SSTL18_II

Regards,

spex

Spex
National Instruments

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