Re: Can I use LVDS (in and out) from those banks which is powered from 3.3V?

Hi Gabor,

If you need to route a 3.3 V single-ended signal to the same bank that is also routing a 2.5 V LVDS signal, I would recommend buffering the 3.3 V signal to 2.5 V and configuring the sbRIO CLIP Generator as LVCMOS_25.

Of course, I only recommend this if it is a requirement that you use the same bank to route LVDS and 3.3 V CMOS. If your application allows, the better option is to use one of the 16 DIO signals that are already 3.3 V, single-ended (DIO_0 through DIO_15). All lines on Bank 0 are powered by VCC_3V3.

Alternatively, if Bank 0 does not work for your application, you can power different bank that is not routing differnetial DIO and power that at 3.3 V. Regardless of if you use all of the banks, you are still required to supply a bank voltage. Since VCC_3V3 is easily accessible already, you can use same supply to power the unused banks.

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