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Veristand scan engine interface use FPGA error "LabVIEW" - Noexistent

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Hello, 

Hello I want to use the FPGA in Veristand. I followed this link to do it :

https://knowledge.ni.com/KnowledgeArticleDetails?id=kA03q000000YGlLCAW&l=en-US

I finished my labview programm, here it is :

 

Grusta07_0-1656591977557.png

 

 I compile it and now I'm back on veristand. 

I added the code on user variable : 

 

Grusta07_1-1656592050305.png

 

I see the variables from the fpga. But when I try to deploy/run, a error comes. I check on the net, and they said to delete the sowftware on the cRIO and reload it. So I did it and come back to Veristand but no difference. 

 

Grusta07_2-1656592100027.pngGrusta07_3-1656592133379.pngGrusta07_4-1656592147123.png

 

Thank you very much for your help 

 

Leo

 

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Message 1 of 9
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Maybe the error that I do is : I delete all the programm on the cRIO and after download all. Maybe I have to delete juste some of them?

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That deployment error could mean a number of things, but most commonly this hints that there's an external file reference (a path to something) in your System Definition that is not correct.

Maybe the quickest way to check for this is go back through whatever System Definition configuration you have done and double-check all of the file paths to make sure they are correct.
The prime suspect would be the disk path to your compiled FPGA bitfile...

Darin Gillis
NI - Chief Product Owner - VeriStand
Message 3 of 9
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Solution
Accepted by Grusta07

Reproduced this problem doing something similar to what you did with User Variables and 3 modules.

 

This error started happening when I began using a Fixed Point (FXP) Type I/O Variable.
By default when a User-Defined I/O Variable is created, and you change to the FXP type, the specific type is set to be 64-bit in size:

Darin_G_4-1656626012966.png


That leads us to this known issue:
     https://github.com/ni/niveristand-scan-engine-ethercat-custom-device/issues/175
which talks about EtherCAT, but now I'm convinced this issue applies to cRIO I/O as well.

Workaround:  Set your FXP type to 32-bits or smaller

Use the Configure Fixed Point... button to change to something like at <+/-, 32, 16> set up like this:

Darin_G_5-1656626091524.png

 

Save, recompile your bitfile, update your System Definition, and then your next deploy should work like a charm.

 

Darin Gillis
NI - Chief Product Owner - VeriStand
Message 4 of 9
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Thank you very much fow your very good answer. So Yes it was the problem. However now, something else appears. 

Grusta07_0-1656684688431.png

I go check on the net, and it said that is caused by wrongs names. However I compiled, recompiled, tried things but nothing is working. https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z000000g1sISAQ&l=en-US

If you know, it will be, I think my last problem 🙂

 

Léo

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That's a new one to me.  
That KB is right on the money though
https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z000000g1sISAQ&l=en-US


Did you use a non-English version of LabVIEW to compile the bitfile perhaps?

Darin Gillis
NI - Chief Product Owner - VeriStand
Message 6 of 9
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I have LabVIEW in english so I suppose that the compile is in english? I know that I have labview 32 and 64 bits 2021 installed on my PC maybe it is the problem to have both? I will retry monday on work. 

 

Thank you for your help 

 

Leo

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I will ask an another question on the forum maybe somebody will know 🙂 

Thank you for your help

 

Leo

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I saw when I compile it is written, compilation labview fpga 2020. But I have labview 2021 maybe it is the problem? 

 

Thank you 

 

Leo

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