Hello to everyone, I'm trying to change hybrid configuration of ethercat chassis in an system definition file that was made by other person. When i replace my bitfile into system definition file I encountered the following error: Error 1401 occurred at Unflatten From String in Modules.lvlibp:RSI Module.lvclass:Read Module Page Property.vi->Scan Engine Custom Device.lvlib:Update Slots.vi->Scan Engine Custom Device.lvlib:Add FPGA.vi->Scan Engine Custom Device.lvlib:FPGA - Select Bitfile (ECAT).vi I've tryed to Veristand version that i'm now using is 2019 R3. Labview Version that I've used for build my bitfile was 2019. Someone can explain ma why happen? Thank you.

VeriStand

Set up of Scan Engine and EthercCAT in hybrid mode

Hello to everyone,

I'm trying to change hybrid configuration of ethercat chassis in an system definition file that was made by other person.

When i replace my bitfile into system definition file I encountered the following error:

Error 1401 occurred at Unflatten From String in Modules.lvlibp:RSI Module.lvclass:Read Module Page Property.vi->Scan Engine Custom Device.lvlib:Update Slots.vi->Scan Engine Custom Device.lvlib:Add FPGA.vi->Scan Engine Custom Device.lvlib:FPGA - Select Bitfile (ECAT).vi

I've tryed to

Veristand version that i'm now using is 2019 R3.

Labview Version that I've used for build my bitfile was 2019.

Someone can explain ma why happen? Thank you.