07-29-2024 11:48 AM
Hi all,
i'm using Veristand 2023Q4 with a PXIe-8881 and GE 5565 PIORC reflective memory board to read and write about 150 channels.
I've noticed that prior configuring the reflective memory with all the cannels I was able to have a stable primary control loop rate at 5 kHz with no late counts increments but when i introduced the reflective memory I'm unable to sustain rates higher than 2kHz without a substantial increase of late counts.
I would like not to reduce the control loop rate (I've a model and DAQ processes that would suffer from the rate hit) and only reduce the reflective memory refresh rate but I don't seem to find the option.
Has someone expirienced this issue? Any fix?
Thank you.
07-29-2024 12:38 PM
The reflective memory problem has always been an issue with VeriStand. The underlying issue is that VS is using a memory location write instead of a block write. This means that you have to perform 150 individual writes/reads instead of one write/read. We had to make a custom device that did block write/reads to handle more than a dozen channels so our PCL would function.
07-29-2024 09:04 PM
Try GitHub - NIVeriStandAdd-Ons/GE-Reflective-Memory-Custom-Device-multiple-DMA-transfer?
Compare to native implementation, that does one DMA transfer per PCL, this custom device does multiple transfers based on memory locations. So the performance of communication with GE reflective memory is improved, when the addresses are distributed in multiple location. Detection change on write is also implemented.
07-30-2024 03:39 AM - edited 07-30-2024 03:50 AM
@Joshe
Do you know if your custom device is posted online or could you make it avalable?
07-30-2024 03:42 AM - edited 07-30-2024 03:50 AM
@ZYOng
I'm aware of this custom device and its on the potential fixes to try out. I'm a little worried about the need to have to update it to LV 2023 and potential compatibility issues that's why i asked on the forum if anybody had a more recent implementation of a custom device solving my issue.
07-30-2024 04:01 AM
Hello, to reassure you, we had to port it to 2020 and 2021 with no issues. We don't have any further version. Anyway, if you have the sources, you can also make changes if required by your performance level.
07-30-2024 10:13 AM
Hi,
I would have to see if company policy allows me to post it, but would need work to bring it up to 2024. I believe it was written for 2013 or 2015. The Git-Hub link looks like it would work for you since it sound like it does the same block writes. Let us know.