We have sinusoidal wave generation with FPGA and acquisition of current sensed voltage signal acquisition with FPGA in veristand project.
But we are observing HP loop count incrementing because of addition of FPGA device. we have other hardware such as PXI6363, PXI2510 and also other models but ensured that those are executing properly and those not causing PCL overrun. Can anybody help what must be going wrong with my FPGA in Veristand
