Re : FPGA-IRQ in VeriStand Custom FPGA VI?!

[HScho]

Hi,

I have built a custom FPGA VI to use in VeriStand. This FPGA VI contains following IRQ:

Now I have also a LabVIEW-VI with FPGA code which I want to use in VeriStand. I have changed it to use it as a custom device, so I removed all the FPGA code and replaced it with indicators and controls so that I can map the Custom Device to the custom FPGA in VeriStand.

But there is still the FPGA-IRQ and I do not know what to do with these two nodes:

How can I use these node in my Custom Device VI or in general in VeriStand?

Thanks for your help.

Regards,

HScho

[Florent_A]

Hi HScho,

Thanks for posting on NI forum.

Can you tell us a bit more about the purpose of your custom device?

there is a native support of FPGA board in NI VeriStand, you may want to read this :

Creating FPGA-Based I/O Personalities for NI VeriStand

Have a great sunday,

[HScho]

Hi,

I have already used a custom FPGA-Based I/O Personality. The FPGA program generates the PWM, reads the Encoder and filter and replicate signals.

I have attached the LabVIEW VI's which I wanted to use as Custom Device. So you think I should add the program code of this VI's to the Custom FPGA-Based I/O Personality?

Regards,

HScho

[HScho]

At the moment I am not using a custom device. I created again a model of the "Motor Velocity Control PIDv2 (RT).vi" and imported it in VeriStand. It seems to me that there is problem with the "RCP sbRIO DC Motor.vi".

If i change the motor voltage inside the subVI the value of PWM Duty Cycle changes. But the value is not present in the main Motor Velocity Control VI.

If I put a probe I can see the value going to the indicator, but the indicator of PWM Duty Cycle is always showing 0....

I have no idea why this happens!

[HScho · Accepted solution]

So finally I have found a solution:

I disabled all of the IRQ stuff. The main problem was that the model I wanted to use in VeriStand was inside a While Loop. I had to remove the While-Loop because VeriStand itself is the loop.

Regards,

HScho