I'm trying to deploy a VeriStand project but I've the error:
The VeriStand Gateway encountered an error while deploying the System Definition file.
Error -50400 occurred at Project Window.lvlib:Project Window.vi >> Project Window.lvlib:Command Loop.vi >> NI_VS Workspace ExecutionAPI.lvlib:NI VeriStand - Connect to System.vi
NI Platform Services: The transfer did not complete within the timeout period or within the specified number of retries.
NI VeriStand: HP Loop.lvlib:HP Loop Main.vi<APPEND>
Complete call chain:
HP Loop.lvlib:HP Loop Main.vi
NI VeriStand Engine.lvlib:VeriStand Engine State Machine.vi
NI VeriStand Engine.lvlib:VeriStand Engine.vi
NI VeriStand Engine.lvlib:VeriStand Engine Wrapper (RT).vi
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
• Unloading System Definition file...
• Connection with target Controller has been lost.
my hardware consists of:
chassis: NI PXI-1042
controller: NI PXI-8110
Module 1:NI PXI-7852R
Module 2: NI PXI-6254
Module 3:NI PXI-6723
I'm using LabView2011 Version 11.0.1f2 and VeriStand version 2011.1.0.32
Starting from the template NI VeriStand FPGA IO PXI-7831R.lvproj in C:\Users\Public\Documents\National Instruments\NI VeriStand 2011\FPGA\Templates I've created my project for my target.
I've modified FIFO properties for my number of elements that are 21 in the case Host to target DMA and 31 in the case Target to Host DMA
Can you help me, please?
Thanks to all
thank you very much for your reply.
Is seems to me that number of packets match, but I'm not sure because it is my first project of this type
Attached my .vi and .fpgaconfig (extension modified in .txt), I would be really grateful if you colud help me
My error was that I used as template file "PXI-7852R Analog, PWM, Digital Lines.fpgaconfig" but the correct one for the project I used is "PXI-7852R Analog, PWM, Digital Ports.fpgaconfig"
Moreover another error was that the size of <DMA_Write> and <DMA_Read> in .fpgaconfig file must be equal to the number of packets and not to the number of elements in the FIFO properties.
thanks to all and specially to Marco!