Announcing VeriStand 2023 Q3

[Brian.D]

It is my pleasure to announce the release of VeriStand 2023 Q3 and related ecosystem packages and utilities.

Release Notes  | New Features

This minor version release includes several notable new features including:

VeriStand Model Generation Support for Importing Non-Virtual Busses as Signals

Use VeriStand Model Generation Support to import non-virtual bus signals from Simulink models as channels. For more information, refer to How VeriStand Imports Models from the Model Generation Support MATLAB Add-on and the VeriStand Model Generation Support add-on documentation.

Python System Definition API

Use niveristand to script system definition (.nivssdf) files for use in the VeriStand Editor and deploy them to the VeriStand Engine. This package now provides a pythonic interface for scripting system definition files. For more information, you can refer to the Getting Started  documentation. Several examples are also included.

Expanded VeriStand.exe Command Line Options

Use the command line to execute processes in VeriStand, including the ability to now open and close specific files or documents in a project. For more information on specific commands and their functionalities, refer to VeriStand Command Line Options documentation.

Support for FMU Logging in VeriStand

Set the logging level for FMUs by editing a configuration file to debug failures. For more information on configuring the log levels, refer to FMI Support documentation.

SEEC CD Support for 3rd-party EtherCAT Slaves with Modules

Added support for 3rd-party EtherCAT slaves with modules in the SEEC CD.

As a reminder, this release builds on the new features and enhancements added in VeriStand 2023 Q2:

Notable Engine Performance Improvements:

• Reduced impact of high channel counts, mappings, and faultable channels on HP Loop Duration. Larger systems can experience reductions of more than 50 microseconds in comparison to prior versions, depending on total count of channels and mappings, and the specific controller. 
• Substantial improvements for systems with a multiplexed DAQ module as the Master DAQ device. 
  • The new default for the PCL DAQ timing source is Signal From Task (Sample Complete). This applies to new projects when the timing source is set to DAQ Timing or Automatic Timing and there is a NI-DAQ device with at least one AI HWTSP channel. Note: this setting has no impact on simultaneous sampled module behavior.

VeriStand Model Generation Support Toolbox supports Importing Signals

• Users can now import signals designated as test points as channels in VeriStand. 

ESI File Importing without installing LabVIEW

• Import an EtherCAT Slave Information (ESI) file into VeriStand using the Scan Engine and EtherCAT Custom Device without installing LabVIE. 

Screen Cluster Arrangement Options

• There are new default cluster arrangement options for VeriStand screens now to compact the appearance of large cluster hierarchies. Select the default arrangement in the VeriStand Editor preferences. 

[FredNiemela]

Is there any hope for updates to the system definition GUI any time soon?

Compared to other NI applications, such as LabVIEW and TestStand, the Veristand GUI seems to be a prototype at best. Some major issues, in my opinion:

• Not possible to use relative paths for dbc-files and other referenced paths. Which makes it harder to cooperate within a team
• The only quick way to edit a system definition file is by using Notepad++ or LabVIEW scripting.
• The mapping diagram? It may be useful for a small example project. But I have yet to see a real-life setup where this can be of any use.
• System configuration mapping window. The source and destination paths are truncated, so you can´t fault-trace without exporting to a text file. (Again Notepad++ to the rescue)

[FredNiemela]

I take that as a no 🙂