# VeriStand

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## 128bit Absolute Time system channel on PXI

Dear community,

at university we have a setup with several PXI systems running VeriStand 2018. These contain one PXI 6683H synchronization module each, which are connected both to a switch with PTP (ordinary network switch) and GPS.

I would like to achieve two things:

1. Get a higher precision absolute time value. The VS system channel Absolute Time contains the entire number of seconds since Jan. 1 1904. Therefore, the subsecond resolution is limited to 10^-6 (least significant digit). In the documentation this value is described as a double coerced from a 128bit integer. Is it possible to extract more subsecond resolution in Veristand somehow?

2. How can I force Veristand to start the primary control loop and thus model execution at exactly a full second? There exists a command for this in the Stimulus Profile editor, but it does not appear to work. It is only possible to start on a full second up to the value of 10^-4. The lower digits of the Absolute time channel value are never 0.

I would be delighted if someone could help me with these problems. I'm a master student working on my thesis. My supervisor tried to find out from his contact at NI, but didn't get an answer unfortunately.

Best regards,

Steffen

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Accepted by topic author steffen_b

## Re: 128bit Absolute Time system channel on PXI

Heya,

For the first question, I can advise you to make a LabVIEW model with the seconds to date/time vi. And regarding the 10^-4 of the second delay to start the PCL is expected in the VeriStand engine.

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## Re: 128bit Absolute Time system channel on PXI

Hey,

thanks for the reply. Good to know that this is expected behaviour in Veristand, at least we can compensate for this if a trusted, accurate timing source is used.

I did some more investigation, and the given time stamp double precision appears to be sufficient.

Best regards,

steffen_b

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