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x310 vs NI-USRP 2942R

Hello,

 

I was reading the datasheets of the X310 and the NI-USRP 2942R.  There seems to be a difference in the DAC sample rate.  According to the datasheet of the x310, the DAC sample rate max is 800 MSPS and the NI-USRP 2942R is 400 MSPS.

 

http://www.ni.com/pdf/manuals/374410a.pdf

http://www.ettus.com/content/files/X300_X310_Spec_Sheet.pdf

 

Is there a difference in the architecture between the two boxes?

 

 

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Hi Jan,

 

The hardware is the same between the 2 units.  The USRP RIO products are based on the X310.  The reason for the difference is because of the software being used.  The LabVIEW FGPA based USRP instrument design library (IDL) uses a 120 MS/s sample clock, where UHD uses a 200 MS/s sample clock to clock the DACs and ADCs.  However, if you are using the host based NI USRP API, it is based on UHD and uses a 200 MS/s sample clock.  There is a 4x interpolation in the DAC which gives the 800 MS/s rate for UHD.  There is a typo in our documentation and the rate should be 480 MS/s for the LabVIEW FPAG USRP IDL based on a 4x interpolation of the 120 MS/s sample clock.  I realize that this is confusing and not well documented, so please post back if you have any follow up questions!

Sarah Yost
Senior Product Marketing Manager
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hi every body ! i am working with usrp x310 and i try modify fpga source but i don't know how create id for radio. tell me please ! thank a lot

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Hi thietnguu,

 

It looks like you have a new question about the USRP x310. Please create a new post for this new question. Also, when you do, please try to clarify what you mean by "create id for radio". The more details you provide will be helpful for us to help you!

Julia P.
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USRP X310 and 2942 have a lot in common.  The USRP-2942 uses the same motherboard and incoroprates the SBX daughterboard.  Because its assembled in the factory we are able to perform CE certification and characterize the RF over 400 points for DC offset, IQ balance, and absolute power level.  We write these values to the EEPROM so that they can be utilized by LabVIEW FPGA to reduce device to device variability.

 

Erik

 

 

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