when does the 2944 hit the shelves?

[art_]

I'm using an X310+UBX-160 with LVFPGA because I need the 200MHz throughput & low latency. Getting it working in LVFPGA has been a real adventure (not in a good way.) I understand the 2944 is going to be the Nationalized version so I'm betting it will play well (or at least better) with LVFPGA. We've got to make plans. When does it hit the shelves?

Art

[muffin.vi]

Hello art_,

The USRP 2944 and 2954 (same version with GPSDO) can actually both be purchased now! You will need to contact your local NI engineer to buy one because they are not yet available for sale online. The 2944 currently works with LVFPGA and LV 2015. The driver for LV2015 and LV Communications will not be released until mid-summer, but a beta driver for LV 2015 can be downloaded on our beta site. 

[True_Boombo]

Hi Muffin,

I have the similar question as Art_. while, I am also interested in which driver will support the 160MHz Daughter board. As, I already heard about that the main problem for 160MHz version is not being supported by the driver.

Thanks a lot!

Cheers,

Bo

[True_Boombo]

Hi Muffin,

I have the similar question as Art_. while, I am also interested in which driver will support the 160MHz Daughter board. I already heard about that the main problem for 160MHz version is not being supported by the driver.

Thanks a lot!

Cheers,

Bo

[muffin.vi]

Hi True_Boombo,

The USRP 15.5 driver will support the 2944 and 2954. You can find this driver on ni.com/beta. 

[True_Boombo]

Hi Muffin,

I applied the approval for using the USRP 15.5 beta driver to test the 160MHz UBX duaghter performance. 

I am using USRP X310 as the based, and installed 2 UBX 160M daughter boards.

With USRP 15.5 driver, X4 MXI cable connected to PXI chassis.

Using Labview 2015 32 Bits.

Testing the boards with Simple Rx Streaming (Host).vi.

I have two questions:

1. In order to run the vi, I have to set the "Wait for LO to lock" in "Configure Frequency.vi" to "F", which is "T" in original setting.

2. After set "Wait for LO to lock" to "F", I can run the vi with maximum IQ sampling rate in 120MS/s rather than 160MS/s

Now, I doubt about whether I am using right FPGA bitfile and right EEPROM seeting to run the system at 160M

So, do you have any experience on using 160M system setting?

Cheers,

Bo

[muffin.vi]

Hi Bo,

I'm not surprised you're seeing issues if you're using a X310 rather than a USRP RIO. In FPGA mode, the X310 typically requires some changes to be usable in LV FPGA. 

Please create a service request at http://www.ni.com/en-us/support.html so that you can talk to an applications engineer. They will be able to better assist you in getting this working. 

[ErikL]

Please contact your local NI field engineer if you have an immediate need for the NI USRP-2944R and NI USRP-2945R.  We plan to make them availble very soon.