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Waveform transmission from FPGA Block memory of Ni usrp 2940R

Hi,

 

I am trying to transmit arbitrary waveform from Usrp FPGA's block memory, instead of transmitting it from host.  For that I had made a block memory and initialized it with my waveform data. I am transmitting the waveform by writing data from memory into target scoped FiFo. Then to transmit on RF, reading from target scoped FiFo on based of digital edge in Tx core Vi

 

The problem is that when I need to transmit the waveform after fixed delay (let say 20us) for 10 times. In start I get 4 or 5 waveform on RF output as desired but then 1 or 2 waveform are missed. 

 

I can not understand why its happening. May be there is the problem in reading the memory. I will be Thankful if you can help me.

 

PS:

1- Block memory initialized with 960 samples of arbitrary waveform.

2- Target scoped FiFo actual number of elements are set to 1025.

 

Regards,

M Mahboob Ur Rehman

 

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Morning! 

 

This is interesting. Sounds like there might be something wrong in the setup of the block memory or the actual code itself to transmit. Have you been able to successfully probe in the code that you're getting all of the data necessary? 

 

Essentially, we want to break this up into two parts -- the setup and the code. I think the best place to start, if it's not time critical, is to remove the hardware entirely and set up a similar streaming application. Try and use the same numbers that you've used to initialize the block memory and the FIFO and then see if you can generate and stream random data and read back, making sure that you're not losing anything that you're expecting. 

 

Once you've verified that you were able to do that correctly, I would then recommend adding your hardware to it. Does that make sense?

Aulia V.
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Hi Aulia V,

 

Sorry for being back here too late. 

 

Although I solved my problem by initializing the block memory with complete pattern of pulses, instead of making pattern by repeating the single pulse.

 

But I am not able to understand your logic of "the setup and the code". If you can explain this approach, I'll try this logic for my future projects.

 

Thanks for your time.

 

M Mahboob Ur Rehman

 

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Hey there,

 

Not a problem. I'm glad you were able to get it figured out. 

 

I referenced that in the context of troubleshooting. We didn't know if the problem was in the setup (so whenever you initiate the FIFO, or maybe it was in the hardware, etc) or if it was the way you were implementing the code. When troubleshooting, feel free to try and see if the behavior occurs in code only (either in FPGA or host) and then when you know that works, feel free to add in the hardware and see if that problem occurs there Smiley Happy

 

Aulia V.
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Thanks for your guidance. Will keep this in mind for my future projects. 

 

Regards,

 

M Mahboob Ur Rehman

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