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Vivado IP Locked error when building X41-X1_400

I am attempting to build an FPGA image, X410_X1_400. I have use branch "master" and "UHD-4.4". I am using Vivado v2021.1 with AR76780. Builds from both branches produce the bit file etc., but give the following error:

 

 

WARNING: [BD 41-1661] One or more IPs have been locked in the design 'x4xx_ps_rfdc_bd.bd'. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
x4xx_ps_rfdc_bd_cpld_jtag_engine_0

 

 

The "report IP status" output say that the IP definition is missing (or something to that effect). However, I can see the IP generated here:

 

 

user1@dev-machine2:~/repos/uhd/fpga/usrp3/top/x400$ ls -lr ./build-ip/xczu28drffvg1517-1e/x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd/ip/x4xx_ps_rfdc_bd_cpld_jtag_engine_0/
total 104
-rw-rw-r-- 1 user1 user1 53576 Mar 29 14:38 x4xx_ps_rfdc_bd_cpld_jtag_engine_0.xml
-rw-rw-r-- 1 user1 user1 38846 Mar 29 14:38 x4xx_ps_rfdc_bd_cpld_jtag_engine_0.xci
drwxrwxr-x 2 user1 user1  4096 Mar 29 14:38 synth
drwxrwxr-x 2 user1 user1  4096 Mar 29 14:38 sim

 


The build.log is attached. I am able to program the X410 and probe it with uhd_usrp_probe. How can I correct this?

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Adding the attachment.

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