Trouble building E310/X310 bitfile (Vivado)

[jason_b]

Hi,

I am having trouble building the bit file for E310 and X310.  Can anyone offer insights into why it doesn't build successfully?  I followed the instructions on the Ettus fpga GitHub but was unsuccessful.  One thing I changed was the line in setupenv.sh that points to Vivado 2015.4.  I changed it to 2014.4.  (Are you actuallying using 2015.4 instead of 2014.4 for your builds?)

I've attached the output of the make process for E310.  Per instructions, I'm using Vivado 2014.4 on Red Hat 6.7.

[ashish.chaudhari]

Hi jason_b,

Are you trying to build the master branch in https://github.com/EttusResearch/fpga? If so, you need to use Vivado 2015.4. The Xilinx IP in master was generated with Vivado 2015.4 and must be built with the same version. When you changed the script pointer to 2014.4, the tools got confused and locked the IP instance:

CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: /home/leeja/fpga-master/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_interconnect/axi_interconnect.xci

The instructions in the manual are for our release branch i.e. maint which does indeed use 2014.4. All of the resources that we publish online are for that branch. The master branch moves forward much more quickly (and is thus considered unstable) and will update its Vivado versions more often. So if you want to build something from a stable codebase I would recommend checking out maint and using Vivado 2014.4. Otherwise you can check out master and use Vivado 2015.4.

Also, after you install the new Vivado version, I would recommend running "make cleanall" before you rebuild to make sure the old build files are wiped out.

Thanks,

Ashish Chaudhari