07-22-2016 11:34 AM
BTW, for the internal signal of OctClock, i think I need GPS antenna and GPS signal to drive the GPSDO inside. As most of my experiments will take place in building, it will be tricky.
I will use on spare USRP to output 10M ref and PPS for others.
Cheers, Bo
07-22-2016 12:17 PM
@True_Boombo wrote:
BTW, for the internal signal of OctClock, i think I need GPS antenna and GPS signal to drive the GPSDO inside. As most of my experiments will take place in building, it will be tricky.
I will use on spare USRP to output 10M ref and PPS for others.
07-24-2016 03:18 PM
Hi Brooks,
I made some more test during the weekend. The results are not optimistic. Here is some quick summary.
First of all, I test the time based example project:
1. Start with 1 Tx USRP, 1Rx USRP, each USRP has two channels. Result: phased and time synced when sampling rate is under 40 MS/s, 40~60 is a grey area, phase locked, but the trigger time will change with seconds interval, the trigger time will become totally unstable with sampling rate over 60MMs/s
2. You mentioned that it may be the problem of the PXI bus. I guess may be it is potential risk part. Though, I have two CPS 8910, but I think the speed of the PXIe slot also matters. I am using PXIe 1082, had 2GB (16G bits) per slot. I feel like it should be enough to support 1Tx and 1Rx situation, but actually not. Anyway, in order to test it, I made some modification in "Rx Code.vi" in the FPGA VI to drop some data in FPGA, to reduce the pressure on PXI FIFO. I have totally make the new FPGA VI running, I created a new topic in this forum about the drop data. Ir always report me "Error -50400 occurred at Invoke Method: FIFO.Read" when I run the host VI, There must be something wrong on the FIFO write logic
Cheers,
Bo
07-25-2016 09:57 AM
Hi Brooks,
Just a quick update about the problem we discussed last week.
Inspired by the point you mentioned that PXIe bus may be the bottle neck. I made some simple modification of the FPGA VI (Not the sample dropping idea metioned in the other forum discussion). Actually, I am not sure whether the PXIe bus is a bottleneck or not, but I suspect that there must timing problem on the FPGA FIFO -> PXI Bux -> Host FIFO chain. So, I change the Rx FIFO depth and TX FIFO depth from 1024 (default value) to 8192 (current setting) in FPGA.
Now, the 4 Tx channels and 4 Rx Channels, the system works will in 120MS/s with good phase locking and time alignment. I ganna testing the 8X8 configuration later.
Thanks a lot for the discussion. It is really inspiring.
Cheers,
Bo
07-25-2016 10:08 AM
Glad to hear your applicaiton is working! One more point:
@True_Boombo wrote:
I made some simple modification of the FPGA VI (Not the sample dropping idea metioned in the other forum discussion). So, I change the Rx FIFO depth and TX FIFO depth from 1024 (default value) to 8192 (current setting) in FPGA.
Increasing the FPGA FIFO sizes can help mitigate overflows/underflows, yes. One thing to note is that if you set the 'number of samples' on the host to a value larger than the FPGA FIFOs, you'll always run the risk of overflow/underflow. If 8192 samples is sufficient, then you're all good. You can also use the default FPGA FIFO sizes and reduce the 'number of samples' on the host to ~1000.