Modify the "Rx Core.vi" in "Streaming Xcvr Sync PPS Trig (FPGA).vi", with FIFO error when run the Host VI

[True_Boombo]

I am trying to modify the "Streaming Xcvr Sync PPS Trig (FPGA).vi" in the NI-USRP Multi-device Synchronized Simple Streaming (NI USRP-294xR_295xR) example project. The main reason I want modify this is that I need to reduce the samples sent to Host due to the limits of FPGA-PXI-Host interface. I want to drop some samples in FPGA, as described in folloiwing picture:

I made modification of the "Rx Core.vi" as shown in the following pciture:

The details of two Case structures in the above picture are:

I also attached the modified subVI in this post.
When I run the example Multi-Device Rx Streaming with Sync host VI, I always receive the following error:

Error -50400 occurred at Invoke Method: FIFO.Read in Fetch Rx Data (U32).vi:7490001->Fetch Rx Data (CDB).vi:2800001->Fetch Rx Data (CDB WDT).vi:3390001->Initiate and Fetch Time (Multi).vi:2060001->Initiate and Fetch (Multi).vi:2680001->Multi-Device Rx Streaming Sync (Host).vi
I believe there there must be something wrong in using the "ready for input" signal of "Write FIFO (Multiple Channel).vi" in the "send 1024 samples to FIFO" case structure.

I need some help to figure out how to make a proper arrangement of this signal, when feed it back to "Input Stream Control.vi"

Thanks a lot!