How to make idle state without completely stop the whole session (usrp 2953 RIO).

[sunson29]

Dear friends, 

I hope I can make the question clear.  My goal is: I have 2 usrp 2943 RIO (lets just say A & B), firstly, A keep sending packet1 to B again and again. B will keep receiving, but at some certain time, B will say to A "sending me packet 2 now", then A will start to send packet2 (packet1 will not be sent anymore).

So far, what I can do is A sends packet 1 again and again, B will receive again and again, and calculate Bit error rate successfully (This means the packet1 can be decoded successfully). 

I don't want to jump to the final goal in one step, allow me to do this step by step.  

So, step 1:  firstly, A keep sending packet1 to B again and again. B will keep receiving, but at some certain time, B will say to A "stop sending me packet 1" , then A will be idle or pause.

after I did step1, then I can do step 2: let A send packet 2 to B.

Here is first question: 

How to make this "idle or waiting" state.  I do NOT want to just stop the whole simulation, this means, when I want to do the step 2, I dont need to re-initial, re-config, blablabla...., start over all session.  Thanks for your help. 

[Case_in_Point]

Hi sunson,

What's stopping you from simply not writing anything on the Tx side? Either writing all 0s for your data or just... not calling Write? On the Rx side you have to initiate and stop Rx sessions in addition to fetching data, but on the Tx side it's literally just you calling Write. So if you don't, the session will stay around and be usable, but the USRP won't output anything. Of course, that's if you're just using the regular USRP driver. If you're using the USRP RIO driver and need to disable from host, Advanced Configure Active Antenna lets you explicitly set the USRP to an Idle state where it disables the Tx and Rx front ends. If you're disabling from the FPGA, then again I think you just want to not write anything.

Cason

NI Applications Engr.