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Generating 160MHz bandpass signal USRP-2953R

Hey Everyone,

 

Wanted to see if there was a way to generate a 160MHz bandpass signal using a uniform white noise generater and broadcasting it through the USRP. My thought is that I can use the noise generator vi and then use a butterworth bandpass filter to filter the noise so that I can generate the wanted signal.

 

To my knowledge, the niUSRP Write Tx Data(poly).vi takes in the data generated by a source. It should take care of the sampling on its own as described in the help dialoge. My issue is that in order to generate the noise, I need to set the noise generater to have a sampling frequency to be 320MHz with 320M samples. This of course is way beyond the limits of sampling LabView can handle. My computer freezes and outputs that the vi is out of memory. 

 

Is there a way to tell the USRP that the waveform I want to generate is noise since the device can handle the workload? 

 

I am using LabView 2015 SP1 and can also do this in the Communication Suite as well.

Device: USRP-2953R

 

 

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Message 1 of 6
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Hi ryro303,

 

First, I recommend doing this on the FPGA, rather than the host if you want to use such high bandwidth. Second, the 2953R can only handle up to 40 MHz of real-time bandwidth (or 120 MHz, depending on the version). You'll need a USRP 2954 or 2944 to get up to 160 MHz. Or did you have a way around this in mind? 

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Eventually this will go on a PXI that supports that bandwidth. Any idea on how to congifure the FPGA to generate this waveform? I only know how to use the write tx data function but it needs data to write. Seeing as the generater is unable to write this data, I need a way to tell the FPGA to do it.

 

Thank you for the reply by the way

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Message 3 of 6
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There is a "generate white noise" FPGA VI in LabVIEW. http://zone.ni.com/reference/en-XX/help/371599L-01/lvfpga/fpga_white_noise/

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Im trying to see if I can download that package as I do not currently see it in my library. This would be awsome if I was able to get this!

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It should come by default as part of LabVIEW FPGA, I believe! 

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