AGC implementation in LabView FPGA for NI-USRP RIO

[User002]

Dear all,

Background: We are modifying based on the simple USRP streaming project, which consists of both host VIs and LabView FPGA VI.

Somehow we need to modify the Rx gain setting at the FGPA level, i.e. in the LabView FPGA VI. Adjust gain setting in the host VI may cause uncontrollable jitter in when the gain become effective on the continuous fetched samples.

Question: But we are not sure if it is possible to adjust Rx gain setting on the fly, and secondly we are not sure what are registers or I/Os for Rx gain controller that we can write data to at FPGA level?

Thanks.

Rui Wang

[HizNI]

What NI hardware are you using?

[wang78]

We are using NI-USRP 2953R as our FPGA target. 

[wang78]

We are using NI USRP-2953R

Rui

[HizNI]

Are you able to change the Rx gain on the host vi? Is there a property node that you have which lets you do that? 

[User002]

Hi HizNI,

Yes, we know that we can adjust Rx gain in the host VI with the aid of an niUsrp property node. But the latency may be too big for us when we fetch data at Rx host, calculate the mean received power, and adjust Rx gain.

so it will be ideal for us if we can move these operations on to FPGA.

Thanks.

Umit

[Peter_W]

Hi Rui and Umit,

Are you wanting to adjust the hardware/amplifier gain settings for the USRP or just adjust the gain digitally within the FPGA?

First of all you need to build some logic to read the power level within the FPGA and decide what level of gain to want to add in.

To do so on the FPGA you can insert another DSP block within the DDC subVI (Rx » Rx Core » DDC Multi-Channel » DDC Single Channel) where the lower level impairments and frequency shift DSP blocks are now:

This is the much easier solution to implement than changing the hardware and should be able to handle most applications. This can also be done in series with the data checking since you can read in samples, check the power level, chose a gain setting, and then apply it to those same samples instead of having to iterate through hardware configurations and checks to correctly tune the gain.

Changing the hardware settings is much more complicated, too much so to explain in a single forum post. I can point you to the right portions of the code to find the register data/address values and what to use to write them but it will require more validation logic to ensure the power reading is accurate (so that you change the gain to the right value), that the settings do change correctly, and that the data you pass along is acquired during a valid state (since you'll be "throwing away" a lot of samples during the gain reconfiguration).

I would only recommend this method for very proficient LabVIEW FPGA developers. If you think you need to go down this route then please contact support@ni.com or call 1-866-ASK-MYNI (1-866-275-6964) and create a service request with an Applications Engineer to start the process.

Best Regards,

Peter W.

RF PSE

[User002]

Hi Peter,

We would like to adjust the hardware/amplifier gain settings for the USRP.

Exactly as you said, we have already started to implement some logics to compute the average received power in the FPGA. The subVIs are great examples for us to follow, because they also involve DSP48E modules to implement multiplication, pipelining the design to allow the compilation in a single cycle timed loop, and four way handshaking protocols etc.

As you suggested, I have also contacted the develop engineer at NI, and hopefully they will help us solve this issue soon. 

We are also thinking about a fall-back solution, where we still compute the updated gain setting in the FPGA, but only send the gain back to the host VI through a front panel indicator of the FPGA VI. So at least we may save time at the host PC, because we do not need to compute the average power and updated gain setting. 

Thanks.

Umit

[wheberth]

Hi all,

I'm also working to implement AGC function (control signal amplitude at ADC inputs)  at the FPGA. 

In a closed loop control approach there is no need for complicated math since the loop controller finds its way to the set point.

Looking at the schematics is possible to see that the RF attenuator control pins (6 bit parallel)  of the SBX/CBX front ends are connected to directlty to fpga pins but we can't find information on how to write to those pins directly from clock driven logic.

Any of you got more information on this?

Best Regards

[Mughees]

Can I generate PWM on one of the AUX I/O pin of ni USRP-2940R.