I am trying to deploy an RT exe to an NI-9047 that uses both FPGA and Scan Interface (hybrid mode) onto a cRIO through SystemLink without the use of the LV dev environment.
I have built the executable, created a package, and deployed it successfully to the cRIO through SystemLink. The issue is when the software starts and attempts to open the FPGA VI reference, the error -61201 is thrown. The details for that error are as follows:
Our current work around is to deploy the chassis through the LV dev environment before installing the package through SystemLink. The issue is also not seen if the rt exe is deployed through the LabVIEW development environment before installing the package through SystemLink (either running built exe as startup or connecting to cRIO and running startup vi).
I am looking for a solution that does not involve using the LV dev environment once the package has been built to deploy and run the RT exe without error.
If you need to use a hybrid mode, I believe the recommendation is to use the NI System Configuration API in your application when it starts up to programmatically set the mode for the slot.
Thanks for the reply,
This is not an issue with the slots being configured incorrectly, I can confirm this through MAX where the programming mode of each slot can be reviewed and set, and they are all correct there.
It is the programming mode of the chassis which seems to be set wrong when deploying through SystemLink. I will have a look through the NI System Configuration API to see if there is anyway to set the mode for the whole chassis there.
Given the options listed for the Hardware Property Node here: http://zone.ni.com/reference/en-XX/help/373107N-01/nisyscfg/property_node_hardware/ it does not appear that the chassis programming mode can be set through the NI System Configuration API, only the mode for the modules.
You are correct, there doesn't seem to be a programmatic way to set the mode for the chassis. If you need to use FPGA mode it seems that the recommendation is to uninstall Scan Engine and only use FPGA mode.