FPGA Timekeeper (Labs): FPGA Timekeeper 1.1b0.zip
Description: The FPGA Timekeeper API is a set of VIs that allow you to synchronize absolute time on your FPGA target. This labs release includes a LVLIB that contains these VIs, as well as several example projects and documentation.
The FPGA Timekeeper API requires the following software components:
The FPGA Timekeeper examples also require the following additional software components:
You can browse the example projects to see examples of how to use the FPGA Timekeeper. There is also additional help found under the Documentation folder in the unzipped location.
I'm sorry your question was not answered before now. If the Timekeeper is never synchronized to a source, it will simply return the time in ns since the VI started. (It's basically just a counter that starts at 0 and counts upwards).
What are the measurement units of "UTC offset" property and "offset from time reference" from FPGA Timekeeper.lvlib:Get Status.vi?
Is there any documentation of the algorithm used in the timekeeper VIs? If yes, is it published anywhere or can it be so that it can be referenced?
As far as I know, there is no public information about the specific algorithm. if you need that information I would recommend contacting customer support, so they can create an escalation with R&D to study the particular scenery and decide what would the most beneficial for both parties. Is important to understand that there are details about what you could expect from the algorithm, that in most cases should be enough to cover your documentation requirements. I am aware that some very specific applications require having the algorithm specific information, but it would require an investigation. I handle a similar case a few years ago, if you want more details, please send me a private message.
I've got a project that is using Timekeepr for years.
I had to change computer and reinstall the my LabVIEW setup. Opening the FPGA code of my projetc it says that it connaot run because 'epoch offset adjustment' and 'time rate adjsutement' are broken.
As the code is protected using a password I cannot see what is really broken inside.
Any help ?
Drivers installed on my machine (Win7 x64) are in the HTML report attached.
Has anyone ever tried to use this on an FPGA that doesn't have a 40 MHz clock? When I try to compile the FPGA code, I get the following error.