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I cannot place the square wave generator express vi in a single cycle timed loop

I am attempting to use the Square Wave Generator Express VI in LabVIEW FPGA module, but cannot compile. I am getting a compilation error stating: "Object(s) not supported in the single cycle timed loop."  I am confused because it also states that the object which is not supported is "Timed Loop."  Attached are screen shots of the block diagram in question, as well as the error message.

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 Hello Jeremy,

 

I tried to recreate this on my end.  I got a different error saying that the Square Wave Generator was the source of the error, only when the VI was configured as outside single cycle timed loop. When configured to be inside single cycle timed loop, I had no problem.

 

Are you sure that you don’t have nested timed loops any where? If not, I would try to delete your timed loop and replace it.  If this does not work, please, Ctrl+U the block diagram and confirm there isn't anything hidden.

 

Regards,

Thomas C.
FlexRIO Product Support Engineer
National Instruments
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I also recommend posting this to the LabVIEW Forums so it gets more viewership.

Thomas C.
FlexRIO Product Support Engineer
National Instruments
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