How to reduce clock skew with TCLK and 2x5673

[serge_malo]

Hi all!

I'm trying to minimize the delay between the Signal Generation of 2 PXIe-5673.

My system is:
Controller: PXIe-8135. Windows 7, 64-bit. NI-RFSG 1.9.8; NI-FGEN 2.9.4
Chassis: PXIe-1075
SigGen #1: PXIe-5673, Slots 2-5
SigGen #2: PXIe-5673, Slots 6-9

I'm using an external Reference 10MHz clock (OCXO).

I'm using TCLK to synchronize the beginning of the Signal Generation.

We would like to tune the Sample clock has indicated in this white paper, so we can get delays in the order of 30-50 ps between the 2 channels.
http://www.ni.com/white-paper/3675/en/

I have 2 questions:
1) For the PXIe-5673, do we need to use an external sample clock to be able to tune the "Oscillator Phase DAC"?

2) In the TCLK Documentation, we can read this to adjust the skew:
Complete the following steps to manually adjust TClk:
a) Configure the devices for acquisition or generation synchronized with the NI-TClk.
b) After acquiring or generating the signal, read the oscillator phase DAC attribute using the individual product drivers for each synchronized device.
c) Store the phase DAC attribute values.
d) Before running the program again, change the program to set the phase DAC attributes to the stored values using the individual product drivers for each synchronized device before calling the niTClk Synchronize VI or the niTClk_Synchronize function.

I'm trying to read the "oscillator phase DAC attribute using the individual product drivers for each synchronized device" for the 5673, but I can't find which attribute this is. I have tried to read
NIRFSG_ATTR_ARB_OSCILLATOR_PHASE_DAC_VALUE. It's always 0
NIFGEN_ATTR_SAMPLE_CLOCK_ABSOLUTE_DELAY. It's always 0
NIFGEN_ATTR_OSCILLATOR_PHASE_DAC_VALUE. It's always 32767

All ideas are welcome!

Regards,
Serge

[Chris.N]

Hi Serge,

I see that you also started a Service Request with us for this issue.  I just replied to your support email, so we can work from there.

Regards,

Chris N.

[serge_malo]

Hi Chris

Your answer has pointed me to the right direction, and my latest test was successful! Great news!

I will answer my question on the Forum.

What I needed to do:

-          Use an External 10MHz clock, split and connected to CLK-IN of both 5450

-          Use an external Sample Clock for the 5673: Setting NIRFSG_ATTR_ARB_SAMPLE_CLOCK_SOURCE to NIRFSG_VAL_CLK_IN_STR

-          Set the NIFGEN_ATTR_EXTERNAL_SAMPLE_CLOCK_MULTIPLIER to 40 (5450 needs a 400MHz Sample clock)

-          Adjust the Oscillator Phase DAC.  I saw in the LabView example that you gave me that this should be set AFTER the Commit call. I set it through the " NIRFSG_ATTR_ARB_OSCILLATOR_PHASE_DAC_VALUE” attribute, but I guess the FGEN attribute would work as well.

-          Set the 5673 to use the PXI CLK as its Reference clock (NIRFSG_VAL_PXI_CLK_STR)

-          Since the normal PXI clock is not very good, I have used a PXI-6672 Timing&Sync card to drive the PXI Clock.

Thanks for your help!