works separately but does not work together

[Sergey(PSU)]

I have faced the following problem.

First I created FPGA vi and Host vi for thermocouple module and signal generation: it works OK.

After that I created  FPGA vi and Host vi for accelerometer-it works as well.

After that  I have tried to combine these 2 bits of FPGA code together: it does not work(it runs but I could not see accelerometer working on a Plot).

I have included the example of just Accelerometer and Generator codes for FPGA vi combined and in a Host vi I did not change anything just left accelerometer.

Can somebody axplain why it does not work combined?

[RER]

Dear Sergey, it sounds like you have stumbled into an interesting issue here (and... by "interesting", I mean frustrating!!) Assuming that it is not particularly large, could I please ask you to post your actual project. Also, could you please provide some additional details on your hardware? What is your cRIO controller/chassis/modules? If I can source some of your hardware myself, I should be able to recreate the issue. This should help me resolve it. Could I also ask about the jpegs you previously attached? Does the FPGA code contain both the Accelerometer and Generator codes? It would probably be self explanatory if you could provide us the code itself. Many thanks,

[Sergey(PSU)]

I have NIcRIO-9072 with: Ni9211; NI9233; NI9263

I have zipped folder with project (it has some rubbish in it but I do not know the way how to save only needed files).

It is the same project as in JPEG files

I could attach working project with Temperature and Signal Generator working as well just let me know.

[Sergey(PSU)]

Did somebody faced similar problem? Or any comments...

[Sergey(PSU)]

Is there any luck?

Did you maneged to source the problem?

[RER]

Dear Sergey,Sorry about the delay in my response, we have been exceedingly busy this week. However, I do have a couple of possible resolutions for you, which involve the rearrangement of a couple of your block diagram objects. The following paragraphs reference the diagrams you posted in your initial message.1.       FPGA vi.jpgThe IRQ interrupt needs to be placed after you have written the data to the “data” queue. i.e. The interrupt should inform the host.vi that data is available on the queue, rather than informing the host that data is about to be written to the queue. Therefore, after you have specified the data rate in frame 1, you should rearrange frames 2 and 3. Additionally, to improve the code further, move the data rate and the mod2/start nodes outside of (nb. to the left of) the sequence structure. Then have the 1^st frame acquiring data and placing it onto the queue. Then have the interrupt in a second frame. You could place the sequence structure (ie. acquisition and interrupt only) in a while loop, and use a shared variable of the “Stop Boolean Control” to stop both loops at the same time. 2.       HOST vi.jpgTo make the previous suggestion work, you will now need to move the ”samples per channel” and the “run” nodes outside of the while loop.  If the FPGA code is held in a loop (as discussed above), then you would not have to repeat the “run” node with each interaction. Please let me know how you get on with these suggestions. The first paragraph of the FPGA.vi notes above should solve your issue. The rest of the suggestions are good design practices, and will improve the efficiency of your code.Best wishes, and thanks for your patience,

[RER]

Dear Sergey,

Sorry about the delay in my response, we have been exceedingly busy this week. However, I do have a couple of possible resolutions for you, which involve the rearrangement of a couple of your block diagram objects. The following paragraphs reference the diagrams you posted in your initial message.

1.       FPGA vi.jpg

The IRQ interrupt needs to be placed after you have written the data to the “data” queue. i.e. The interrupt should inform the host.vi that data is available on the queue, rather than informing the host that data is about to be written to the queue. Therefore, after you have specified the data rate in frame 1, you should rearrange frames 2 and 3. 

Additionally, to improve the code further, move the data rate and the mod2/start nodes outside of (nb. to the left of) the sequence structure. Then have the 1^st frame acquiring data and placing it onto the queue. Then have the interrupt in a second frame. You could place the sequence structure (ie. acquisition and interrupt only) in a while loop, and use a shared variable of the “Stop Boolean Control” to stop both loops at the same time. 

2.       HOST vi.jpg

To make the previous suggestion work, you will now need to move the ”samples per channel” and the “run” nodes outside of the while loop.  If the FPGA code is held in a loop (as discussed above), then you would not have to repeat the “run” node with each interaction. 

Please let me know how you get on with these suggestions. The first paragraph of the FPGA.vi notes above should solve your issue. The rest of the suggestions are good design practices, and will improve the efficiency of your code.

Best wishes, and thanks for your patience,

[Sergey(PSU)]

Dera Rich,

thanks a lot for suggestions.

About IRQ: I already had this suggestion from another member on this forum, so I already have tried it for just accelerometer.

After placinq IRQ interrupt into 3rd frame the code stopped to work. Anyway  I am compiling changed code now and we will see in a couple of minutes time if it works.

I understood what to do with IRQ and mod2/start but what about "Then have the 1^st frame acquiring data and placing it onto the queue. Then have the interrupt in a second frame. You could place the sequence structure (ie. acquisition and interrupt only) in a while loop, and use a shared variable of the “Stop Boolean Control” to stop both loops at the same time. "Can you ex[ploain it in more details, or just make an example of the code or changes to VI I have posted so I could copy it.

Another question: I have used an example from LabView for accelerometer and IRQ was in 2nd frame. Second time I hear about changing its position. Does that mena that example supplied with NI is not optimal?

[Sergey(PSU)]

I have attached the code with changes your suggested without (Then have the 1^st frame acquiring data and placing it onto the queue. Then have the interrupt in a second frame. You could place the sequence structure (ie. acquisition and interrupt only) in a while loop, and use a shared variable of the “Stop Boolean Control” to stop both loops at the same time. )

I have tried to run it but it still behaves the same(probably because I did not finished all the changes your suggested) . Could you, please, take a look again.

[RER]

Hey Sergey, 

Please see the attached screen capture of the reworked FPGA.vi. Because we have used a while loop, we do not need to call the mod2 to start with each iteration.

Furthermore, because this is now in a loop, you do not need to call the “run” node on the host.vi with each iteration if the host.vi while loop. Therefore, you can move the “samples per channel” and the “run” nodes outside of the while loop. (i.e. everything to the left of the “wait on IRQ” node needs to be moved outside of the loop).

This means the run is only called once.

Please let me know how you get on.
Best wishes,