Real-Time Measurement and Control
synchronous data generation
Javed,
With that particular module the short answer is no.
Timing on the FPGA can be achived in a couple different ways. The default clock rate for the FPGA diagram is 40 MHz. So any normal loop timing is based on the 40 MHz or 25 ns clock rate. For your given frequency the closest clock rate based on a 40 MHz loop would be 58 iterations which comes out to 1450 ns or 689.655 kHz, an error of about 0.223%.
The second option is to created a derived clock which is an integer ratio of the default 40 MHz. This allows much more custom clock rates. For example a derived clock rate could be 11/17 of 40 MHz, which would be 25.882 MHz. The numerator and denominator of the ratio must each be in the range of 1-32.
The derived clock can be used to control the timing of the Single Cycle Timed Loop (SCTL) in the LabVIEW FPGA diagram. The SCTL runs once for each tick of the derived clock. The derived clock can not be used to drive any other part of the LabVIEW FPGA diagram. Therefore the code you want to run at your custom clock rate must work inside of the SCTL. However, due to the interface between the FPGA and the NI 9403 module, this module can not be used inside of the SCTL.
One option would be to use the NI 9401 module (8 channel TTL DIO) instead. This module can be used inside of the SCTL. For your application the best derived clock rate would be 31/26 of 40 MHz which is 47.692 MHz. This rate is 69x your desired clock rate. Therefore you can run the SCTL at 47.692 MHz and update the output of the 9401 module every 69th loop iteration. The actual loop rates come out as follows:
Derived Clock Rate: 31/26 * 40 MHz = 47.692307 MHz
SCTL Divider: 69
Actual Clock rate for the DIO: 47.692307 MHz / 69 = 691.193 kHz
The error between this clock rate and your desired clock rate is 0.00103% . This is well within the specified accuracy of the clock on the FPGA.
The attached VI can be used to calculate the possible derived clock frequencies for the FPGA and also determine the optimal (most accurate) derived clock frequency for a specific desired rate.
The only other caveat to consider when calculating derived clock rates is the maximum clock rate possible for the code inside of a SCTL. Based on the complexity and nature of the code you have inside of the SCTL there is a maximum possible clock rate for which the loop can be compiled. The derived clock rate can not exceed this maximum. 80 MHz is a good estimate for this maxium although very simple designs may compile as high as 120 MHz, while more complex code may only compile closer to 40 MHz inside of a SCTL. The attached VI provides the option to set a maximum derived clock rate to consider.
Javed,
Since you have chosen the 9403 module I assume you are adding your own RS-422 to TLL converters.
Acquiring the data at 691.2 kHz based on the external clock should be fairly trivial as you can easily oversample all signals, look at your clock and store/buffer the data whenever you see a clock edge (rising or falling depending on your particular situation). However, this will not be possible with the 9403 module you have, as that module is not fast enough for the rate you need. You should use 2 9401 modules instead (8 channels at 10 ns). The 9401 can be sampled much faster and can also update signals much faster than the 9403, though it has fewer channels. The channels on the 9401 can be configured for input or output in two groups of 4 channels, i.e.. 8 out, 8 out or 4 in and 4 out. This configuration can be changed at run-time programmatically.
If you have the 9401 and want to generate signals at 691.2 kHz use the method I describe earlier. Since you want to generate a 691.2 kHz clock signal, you will actually need to update at least that one channel twice as fast (1.3824 MHz). To create a SCTL running at that rate you should configure a derived clock at 53.913 MHz (40 MHz * 31/23). Then configure the SCTL to update your outputs every 39th loop iteration. For the clock signal simply invert the output every time. This will generate a clock signal at 691.2 kHz based on the 40 MHz FPGA clock. (The actual frequency based on the math will be 691.193 kHz. This is well within the accuracy of the 40 MHz clock on the FPGA.) For the other data channels you will likely pass the data from somewhere else to the SCTL using either a FIFO, DMA or memory block. In the SCTL you will read the next set of data every 78th iteration and update the outputs.
javs24_1 wrote:
Is there any module with built in Convertor so I would not have to go in the hassle of making a custom board.
Unfortunately right now we do not have any modules with the built-in converters. The 9871 module, which is a RS-422/485 module, is based on a UART and only support serial communication. It does not offer progarmmable DIO using the RS-422/485 electrical interface.
