synchronization two fpga 7962r digital output

[heywanna09]

Hi!

I am using two FPGA 7962R (flexrio) with each 6581 terminal board in PXIe-1082 chassis. My problem is how to synchronize two 7962R digital output with PXIe-1082 chassis backplane signal Dstar* or Clk10 or DAQ signal.

Actually I tried the synchronization with one DAQ counter clock (confering 'Gen Dig Pulse Train-Finite_NI. vi') , and get the signal PXI-Trig0 by source terminal and target terminal connection, but that one does not work properly. Especially, one trigger signal in HOST to set the starting point of each FPGA (7962R), make error by depending on the trigger signal value(Hz value and Timed loop clock in FPGA vi). It was very tricky and not reliable.

My aim is simply to use two FPGA 7962R Digital output as one FPGA, for controling X-axis, Y-axis with each FPGA, while able to change each FPGA (X-axis, Y axis) digital output value. Because the synchronization is not correct, X,Y axis control with Two FPGA currently is out of target if I use simply while-loop design in HOST and timed-loop design in FPGA vi. What is correct design to synchronize the two FPGA 7962R without using PFI line, only with PXIe-1082 chassis backplane signal and able to change the digital output value? Please let me know any idea for HOST vi, FPGA vi programming.

Best 

[Haagen-Dazs]

Hi heywanna09,

It is possible to sychronize the two FPGA clocks as described in this article:

http://digital.ni.com/public.nsf/allkb/53306F0FDA486B298625738A007B130F

From what you posted I believe this is your best bet. Please let me know if this is not what you were looking for.

[heywanna09]

Hi Patrick,

There is no such menu as 'Synchronize FPGA clock to PXI_CLK10' in labview 2012 and FPGA 7962R.

If the newer version labview (2012) support automatic CLK10 clock synchronization in FPGA 7962R,

how to properly set the synchronization in HOST?

Let me explain my situation again.

FPGA1 - x control, FPGA2 - y control, (FPGA1, FPGA2 are same model 7962R with 6581 DIO)

x array datainput, y array datainput -> it goes to Digital output

x0,   y0

x1,   y1

x2,   y2

.............

I want to run the array set as (x0,y0), (x1,y1), (x2,y2).....  to two FPGA,

but the synchronization does not work, the array set work like (x0, y2), (x1,y0), (x2,y1)..... this is problem!

Actually, if I set y value to y0 as one value, the DIO work properly (x0, y0) (x1,y0) (x2,y0)......, the system works good (I have checked)

FPGA1 runs own loop with timed loop or wait loop, independantly, FPGA2 runs own loop with timed loop or wait loop.

Host.vi datainput ((x0,y0), (x1,y1), (x2,y2).....) in loop feed the value to each FPGA, but FPGA.vi does not synchronize, two FPGA DIO works like  randomly (x0, y2), (x1,y0), (x2,y1)..... or some weird sets.

Best