sbRIO synchronism IO and VIs

[Jer hello]

Hello,

I'm coding a program on a sbRIO. It is a program that I wrote for a cRIO and now I'm putting it on an sbRIO.

The 'problem' is that there is no scan engine support for the sbRIO, so I've got to use the FPGA to access the I/O.

So I've been accessing the IO using the open FPGA function, scanning the IO reading/writhing to shared variables in a timed look (1Mhz) VI which sits on the FPGA. On the Host I've a master VI calling several other VI's which read the shared variables and write to them.ost have to do its own

But the timing seems to be all out of sink and very erratic, because I guess the VI's running on the host processor take varing lengths of time to run, or something like this?

Is there some standard structure to scan the I/O writh it to shated variables and then allow VIs to manipulate the shared variables which

are written back to the IO by the FPGA program?

Or does each VI on the host have to its own accessing of IO individually?

Ideally I like to have the same functionality as the scan engine provides for the cRIO, even at 10Mhz scan.

Any suggestions, examples, standard architecture solutions?

Thank you,

Gabriel

[AdnanZ · Accepted solution]

There are three methods you can use to communicate between host and FPGA which are mentioned over here:

http://zone.ni.com/reference/en-XX/help/371599F-01/lvfpgaconcepts/pfi_data_transfer/

Once you get this done, then it's up to you as to how you want to relay this data to other subsystems. You could use shared variables, native TCP/IP protocol, queues etc. to transfer data to other VIs on the same machine. So, one VI or loop on your host can be used only for communication and the other VIs can 'wait' to receive data.

[Jer hello]

Thank you Adnan,

Yes there is probably a solution in what you have said, thank you!

The 'Host' is the Real-Time controller on the sbRIO, Yes the DMA solution suggested, is probably a good one.

Thnaks for the pointer, I will have a look for a good example, if there is any example that you recommend, please do.

Thanks again,

Gabriel

[AdnanZ]

Go through the shipped examples (Help -> Find Examples) and there are a few pointers there. Start developing your application and do ask questions along the way.

[Spex]

Hi Gabriel and Adnan,

With LabVIEW 2010, we added support for Scan Engine on NI Single-Board RIO.  The fixed personality Scan Mode supports all Single-Board RIO devices with 2M Gate FPGAs.  On supported devices, the Scan Mode supports the onboard analog and digital I/O modules (modules A, B, & C in the LabVIEW project), but you will need to use FPGA programming to access the 110 onboard DIO lines.  For devices with smaller FPGAs, you can program a hybrid combination of FPGA logic with features from the Scan Engine, including IO Variables with their synchronization capabilities or support for plug-in C Series. 

Regards,

[Jer hello]

Hello Spex
Thanks for the update, I agree that its a big step foreward, scan engine removes a lot of work for the designer.

I've a sbRIO 9632.

I've downloaded (dragged down...slow...) LV2010, I could not find the 'NI-RIO CD' on the labview download page that the installer requested, but

things appear to be working OK so far...

I have scan engine access to analogue IO.

So I added an FPGA target to the project.

I get the message adding an FPGA puts the target into Labview FPGA mode... and it appears the scan engine stops working.

I thought that the FPGA could only hold one bitstream i.e. scan engine or custom FPGA code but not both, I hope that I am mistaken.

Perhaps I am missing some setting or procedure, any example floating around, with scan engine to access analog and somewhat synchronous (real-time-ish) FPGA supported DIO access?

Thanks for your help!

Gabriel

[Spex]

Hi Gabriel,

It is true that the access to the FPGA has two defined modes, Scan Mode and FPGA mode.  When used in FPGA mode, you can compile features of the Scan Engine into your FPGA bitfile (some people are calling this hybrid mode).  The following knowledge base should provide information on how to manage which modules are using scan engine features versus modules or I/O that is dedicated to the FPGA access. 

http://digital.ni.com/public.nsf/allkb/0DB7FEF37C26AF85862575C400531690

The final trick to getting scan engine working from FPGA mode is compiling the FPGA VI and ensuring that you use an "Open FPGA VI Reference" function on your RT host so that the bitfile is deployed to the FPGA with the scan engine and FPGA logic.

You can also use the scan engine to synchronize your DIO with the scan by implementing User Defined IO Variables.  User defined IO variables are covered in the LabVIEW help here:

http://zone.ni.com/reference/en-XX/help/371361G-01/lvioscanhelp/io_vars/

Regards,

[viScience]

Hi Spex - I was told that sbRIO had no scan engine support and thus could not be used with softmotion.  It appears that this is at least partially untrue.  Could you confirm which components of softmotion can run on the sbrio?

Thanks,

Mike Sachs

viScience.com