sbRIO-9607 FPGA_VIO 3.3V startup time

[dkorobkov]

Hi all,

Merry Christmas and Happy New Year to everybody!

I built a custom extension board that is stacked under sbRIO-9607(06). I use 5V ( RIO Mezzanine Card Connector pins 54, 60, 66, 72) for supplying most of logic and FPGA_VIO ( 3.3V, RIO Mezzanine Card Connector pins 234, 240) to feed chips that interface to FPGA pins.

When I power up the board it lseems that 3.3V appears on FPGA_VIO pins with 200-250 ms delay after 5V appearing on 5V pins. In my current schematics this causes glitches on system power up that severely affect the connected hardware.

I did not find any statements in user manual about this delay. I found only obvious statements about floating DIO lines and FPGA_CONF pin.

Did anybody meet the same problem? Is this behavior by sbRIO design or my sbRIO-9607 board is bad? Is the maximum delay time specified anywhere? Are there ways to minimize this delay?

In the next release of my PCB I will handle this case but I need some solution urgently.

Thanks in advance.

[eltico]

Hi,

Merry Christmas and Happy New Year to you too!

This delay seems pretty long but it makes sense as the 3.3 V pins are obtained by reducing the 5 V power source. It probably doesn't appear in the manual because it's a quite specific application.

If you need to "synchronize" the voltages, the best way is developing a conditioning stage in the input of your circuit. 

Regards.