microsecond timer loop in RT VI not working

[Sridhar.Ramesh]

Hello,

I am using a cRIO-9012 with Chassis 9101(FPGA Interface programming-only) and a 9623 Voltage AO module as a beginner.

Also read-up some literature(very limited) on the controller.

Using Labview 2011, i am trying to create an RT VI to toggle b/w 0V and 5V on the 9623 (using a user-defined FXP variable). With this, i was hoping to find out the execution time of my RT VI.

There is no Host VI. RT VI is included directly under the cRIO Target in the project, while an FPGA VI is included under the FPGA target.

Currently, the RT VI contains nothing but a timed loop in which a case structure toggles a value b/w 0 and 5 as input to the user-defined variable.

In the FPGA VI, meanwhile, i coded a continuous while loop that pipes the user-defined variable to the AO1 of an FPGA I/O Node.

My questions are as follows:

a) At what speed does code execute on the RT VI? (Given that 400 MHz PowerPC is the cRIO processor)

b) If i configure the timed loop to take a 1MHz clock source and set the period to below 1 ms (count of 1000), RT VI simply breaks communication with my PC and doesnt appear to be executing at all (AO line doesnt toggle). I read somewhere that full-blown CPU usage could cause this. So IF it is possible to get control loop times on the RT VI < 1 ms, could somebody guide me on how tis is done?

Seeking insight..

Thanks & regards,

Ramesh

P.S. : Apologies for not posting any VIs. Labview is on a Stand-alone PC that cant be connected to LAN presently.

[Sridhar.Ramesh]

Hello,

I went through an extensive search on the various threads in this forum related to micrsecond timing.

a) In one of the discussions, a developer had modified parameters of the .ini file on the RT target using FTP. This was for a different controller but i decided to try the same thing with my RT. Although configuration change was accepted smoothly, futher monitoring STILL showed me that RT loop execution was at BEST 1 millisecond.

b) I also tried switching to Scan mode and up-ped the conversion time to less than 2 us and failed to get any positive results.

Any attempted loop time of less than 1 ms results in wildly fluctuating loop times (all >= 1 ms).

c) Since it is possible to scale down FPGA clock of cRIO 9012 by 16 (max), I also tried running the FPGA clock at 2.5 MHz and searched for ways to use this clock for my RT timed loop as source without success.

Can someone please confirm that it is NOT possible to use a 1MHz clock source on my cRIO 9012 RT if i do not have any other NI clock-generating hardware?

My present h/w config as follows:

1) cRIO 9012

2) 9101 chassis

3) 9263 4-channel voltage AO module