I am using IEC 61850 merging unit example Lab View project. I duplicated that project and modified according to my requirement. Some additional errors are there in my duplicated code. Please see the below attachments. any training module for understanding this merging unit code and help to remove these errors will be appreciated.
I am using LabVIEW 2015sp1 version and IEC 61850 15.0 package.
I repeated the implementation you tried to follow based on the SMV Merging Unit example and found the two possible mistakes that could have caused this.
1. The error you see in Screenshot (30) is caused by the indicated control not being available in the FPGA code (Generate Sample (FPGA).vi). You may have deleted or renamed the "Channel #1 FIFO Overflow.?" indicator. You should note that the indicator's name has a line break after the "1" character. If you do not want to rename the indicator, you can try to delete the "FPGA VI Reference" indicator and place it back. That will contain a list of all indicators with their current names.
2. You get this probably because you tried to address the issue above using the method I mentioned. Once you remove an indicator from the front panel, its terminal link is also removed. You can address this by clicking on the top-right terminal entry on the module (indicated on the "Terminal Location" image attached) and then clicking on the FPGA VI Reference indicator you have in the front panel. That way, the error you indicated in Screenshot (31) should be addressed. If you do it this way, however, the naming issue will most likely carry on to the VI's downstream, so I would recommend addressing issue #1 by adding a line break to the indicator name.
I don't think that there are any training modules for the IEC61850 module, but you can learn a lot by experimenting with the examples.
I hope this information has been useful.