cRio FPGA read 1024000 samples and transfer to RT

[valentina.alina]

Hello,

I have a cRIO application and i have to read 1024000 samples, on 3 channels at a sampling rate of 25.6 khz..  My NI 9232 offers the posibility of sampling at such a rate. The problem is that i do not know how to aquire and transfer that amount of data to the RT.  I'd be grateful if someone could help me.

[Tunde_S]

Hi Valentina,

You should use FPGA to Host DMA FIFOs to have a lossless data transfer between your FPGA and RT targets.

There are examples that show how to set this up. You can find these examples in the Toolkits and Modules >> FPGA >> Fundamentals >> Data Transfer and Storage >> FPGA to Host section of the NI Example Finder.

Also, white paper article 4534 provides instructions for configuring a DMA FIFO to transfer data from your FPGA to its host.

Regards,

[valentina.alina]

Hi Tunde_S

I have modified the code on the FPGA and on RT target but it is still not working. When i run the RT.vi it should automatically start the FPGA.vi too, but it doesn't and no data is transfered.

[Tunde_S]

Valentina,

Based on how you designed your application, you should set the Samples per Channel to 1. You are running the FPGA VI by calling the Run method in a loop in the RT.vi. Each time the FPGA VI runs, it writes 1 sample from each channel to the FIFO. The default value of the Samples per Channel control was 1000. If you set this value to 1, does your application output data?

Were you able to successfully run the example applications that I pointed you to in my previous post?

Regards,

[valentina.alina]

I already tried that but it does not read anything. If i use the probe to debug, the wire that connects the data is shown like this:  []

I run a couple of examples you pointed out and they were ok. The problem is that if i design my application exactly like in those examples, it is still not able to read that amount of data.

[Tunde_S]

Valentina,

A probe value of [] indicates an empty array. You’ll get an empty array from the FIFO Read method, if it times out and there is no data in the FIFO.

If you want to avoid this, you need to place the FPGA Abort method as the last node in your while loop. If we look at the help documentation for the Run (Invoke Method), it states that if the FPGA VI is already running on the FPGA target, the Run method does nothing. In other words, it is possible that you looped back to FIFO Read method, before restarting the FPGA VI so that you can write new data to the FIFO.

Also, I believe the large RT FIFO timeout of 50 seconds makes it seem like your application is not transferring data, through the FIFO. The RT FIFO will wait until you've transfered N samples from the FPGA FIFO to it. If the number of samples that you transfer from FPGA VI not greater or equal to the number of elements you request from with the FIFO Read method, you're RT FIFO will always wait 50 seconds before it times out. Based on how you designed your FPGA VI, you'll only get 3 samples from the RT FIFO each time the FPGA VI runs.

Regards,

[valentina.alina]

And if i set the Samples per Channel to 1 , where do i specify that i want 1024000 samples? I also need these 1024000 samples to be read in a continuous way: first 1024000 samples, aflter the reading is complete, read another 1024000 an so on...

[valentina.alina]

This is the laterst version of the program. It lets me read about 40.000 samples at a continuous and decent rate. However i am not very confident that i do not lose any sample.

[Edit]: if i add the abort node the reading is not continuous. All the charts are cleared, the data acquired appears as [] between every two consecutive readings.

[Tunde_S]

Valentina,

You are correct to mention that your data will not be continuous with the abort node. I only mentioned that you should use the abort node because your FPGA VI was not sampling continuously and you were restarting the FPGA from the RT target.

If I understand your application correctly, you’d like to continuously analyze a set of 1024000 samples on the RT target. Is this correct?

If so, why are using a For Loop to read from the AI node only N times (where N = Samples per Channel)? Why not place the AI node and FIFO Write method in a while loop, as done in the Streaming Data (DMA).lvproj example, which you can find in the LabVIEW Example Finder? By placing these nodes in a while loop, you’ll get a continuous stream of data from the FPGA until you tell the while loop to stop.

On the RT side, you can also use a while loop to continuously read the data in the FIFO. If reading 1024000 samples from the FIFO at once does not work for you, you should consider setting the number of elements to read from the FIFO to a value where 1024000 is a multiple of it. This approach might take a little more work because you have to join N iterations of the FIFO data together in order to pass a set of 1024000 samples to your analysis function.

Regards,

[valentina.alina]

On the fifo part, the maximum number of samples per channel that i can read without getting the error that the fifo is full is 1000. If i  try to read 1024 times 1000 samples, it will take forever... and the reading part is not the only part of the project. The reading part should be the fastest, and i need all the samples to be available at once.