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[cRio] 9063 - First Analog Input FPGA program

Dear All

 

I am quite new in FPGA programming. I read the FULL CRIO DEV GUIDE. I am using Labview 2017 and CRIO 9063 and NI9205.

I don't have any problems with communicating with NI 9402 and creating vi using in/out from 9402.

 

My plan is to create acquisition/control program for four signals (f>1kHz), four digital outputs and 6 signals (DC or AC 50 Hz).

 

1. Quick question why i don't have an option to set a voltage range for 9205? (screenshots in attachment). https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z0000019Lp7SAE

 

2. 2nd quick question when I am using a FXP type from AI0 - is this value in volts? Is it automatically adjust based on voltage range which I would like to set in point 1 🙂 ?

3.. I created a simple test circuit (schema below). I tried to measure a simple 50 Hz sine signal from Textronix signal generator. I set a frequency to 50 Hz and Vpp from 0.5 V to 3 V.

The signal which I received is most of time nothing and sometime something similar to sine but the signal is cut off on values -1,1 (no matter what value is set on signal generator).

 

Where is the issue? I spend a lot, lot of time trying to fix it. I will be glad if someone can help me. 

 

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  1. There is range settings. You can't see the setting?
     How Do I Correctly Use Differential Mode on an NI-9205, NI-9206 or NI-9209 On My CompactRIO?
    Right click on NI 9205 in Project Explorer and select "Property"

  2. 9205 returns voltage data. You shouldn't transfer acquired data using I16 FIFO. Use FXP corresponding to AI data type.
    Default, the FXP type is <+/- 26,5>. You can know the type using Detailed Help (Ctrl + H).

  3. I believe using FXP may resolve this problem
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GCentral
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Hi

 

Thank you very much. It helped.

 

But I have another challenge now.

I am trying to build a acquisition program. 7 different signals should be measure, all with the same sample rate and all have the same one trigger. The hardware is the same as before.

I prepared two vi's MAIN_(PRE_TRIGGER.vi and acquisition with pretrigger.vi. When I am using those two programs I am able to acquire 1000 samples. The goal is to acquire 7 signals with sampling frequency  equal to 30 kHz. 

1.What should I do to acquire more than 1000 samples?

2. How should I extend a program to acquire more 7 signals instead of one? Should all signals be in the same loop or should I prepare a separate loop per analog input in FPGA vi?

3. Is there a possibility to acquire 3 times 1000 samples without losing any samples?

4.If I would like to acquire 3 times 1000 samples what is the best idea to create one 1D array with samples? Should I change a tunnel mode to concatenate?

5.The output of MOD1 AI0 is FPX where word length is 26 and integer part is 5? Can I change it to different values to limit a size of sample in bytes?

6.What is the best idea to stop the loop with acquisition in host vi? Should I check how many samples was received and if the values is equal to for example 300 for each of channel the stop program?

 

Thanks for help

 

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Hi

 

Thank you very much. It helped.

 

But I have another challenge now.

I am trying to build a acquisition program. 7 different signals should be measure, all with the same sample rate and all have the same one trigger. The hardware is the same as before.

I prepared two vi's MAIN_(PRE_TRIGGER.vi and acquisition with pretrigger.vi. When I am using those two programs I am able to acquire 1000 samples. The goal is to acquire 7 signals with sampling frequency  equal to 30 kHz. 

1.What should I do to acquire more than 1000 samples?

2. How should I extend a program to acquire more 7 signals instead of one? Should all signals be in the same loop or should I prepare a separate loop per analog input in FPGA vi?

3. Is there a possibility to acquire 3 times 1000 samples without losing any samples?

4.If I would like to acquire 3 times 1000 samples what is the best idea to create one 1D array with samples? Should I change a tunnel mode to concatenate?

5.The output of MOD1 AI0 is FPX where word length is 26 and integer part is 5? Can I change it to different values to limit a size of sample in bytes?

6.What is the best idea to stop the loop with acquisition in host vi? Should I check how many samples was received and if the values is equal to for example 300 for each of channel the stop program?

 

Thanks for help

 

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Hey, don't create so many FIFO for each AI channel.
Read this HELP page. You should transfer multiple AI data through one DMA FIFO.
Transferring Multi-Channel Data in DMA Applications (FPGA Module)
This method is the best way 🙂 You can know how many samples are already acquired so, can stop the loop.

help.PNG

 

 

 

 

Next, to understand FXP, read this help.

Numeric Data

In this case,

integer word length = 5bit
word length= 26bit

Looking into Property for the constant/control/indicator is the best way to understand the configuration.

 

And you cannot change the FXP configuration.
Of course, you can select FXP (Voltage) or INT (not calibrated, raw value) in module property page.

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GCentral
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hello, I would like to transfer multi analog signal (50 Hz) from FPGA to real-time LabVIEW. 

 

I run the example  Transferring Multi-Channel Data in DMA Applications (FPGA Module),

however, I cannot see any signal at the front panel.

how can I determine samples to read per channel and loop time? or is there any example? 

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I recommend you start a new thread. It would be useful to know what hardware you had.

FYI, this is my favorite example
http://www.ni.com/example/31206/en/

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