I recently made a small change to my FPGA code on a cRIO, and it resulted in a Timing Violation compile error. Basically there were two constants in my code that I wanted to change to controls so that I would be able to change these values without recompiling every time. In the attached photo, I've circled these two constants in red. Originally these constants were contained in the SubVI (subVI is in the lower of the two windows), but I pulled them out into my base FPGA code, and then replaced them with controls so that I would be able to access and change them from the Host VI. Unfortunately, changing these to Controls resulted in a timing violation, giving me an achieved rate of only 33MHz or so.
As you can see, my code isn't exactly very intensive. Although maybe I'm making an FPGA faux-pas somewhere? Any ideas as to what I should do to improve my situation? Is it possible there's a problem with the SubVI? Should I just copy and paste that into my base VI rather than use a SubVI? That SubVI had already been saved on my PC, and I brought it into my FPGA code by right-click>"Select a VI...". Is this not the right way to do it?
Thanks a lot for your help.