Is it possible that run fpga vi one time to intialize the readout analog channels and put data to DMA fifo and run RT vi to correct data from DMA fifo read because I just ran the code that collecting the data in realtime without running fpga vi over and over again(just instialize one time) unless all the second, third time and go on just the same data. Thank you.
I read your post and seem to understand that you want to run the FPGA VI only once for initialization and then collect data from your RT VI several times without running the FPGA VI again. Please let me know if I am missing anything here. Also, what kind of data are you collecting from your RT VI. If you can describe your measurement setup to me somewhat, that would be great. Thanks!
That is correct. I am correcting the data from analog input modules 9221The problem that i saw is when I ran the RT vi but the FPGA vi is not running eventhough the data has been collecting on the FPGA fifo. So. I am not sure whether the fpga vi physicly need to run on the front panel to be able to get data. or the reason that fpga vi is not run even I check run fgpa vi form "open fpga vi reference" because i didn't request any indicator from fpga vi. Is this clear to you?
A solution to this could be to set your FPGA VI to run when the cRIO is powered so that you do not have to depend on opening the FPGA front panel. You will find the instructions in this KnowledgeBase with the exception that I would choose Autoload VI on device powerup. Hope this helps.