Hello all the LV experts,
Just like the subject suggests, after cRIO 9073's software update from older version to 17.0 version, I am running into problems such as not loading ini values and all the real time status returns NaN.
Perhaps, you can let me know what I did was wrong.
1. I updated its software using MAX but without formatting the disk. I just directly installed it without touching ANYTHING(ex. didn't turn the Safe mode on during this software update).
2. It already had a working rtexe but after the update, I built its RT again and uploaded the new rtexe acquired from the new building and the problems began happening.
3. In my attempts of fixing it, I re-compiled its FPGA.vi(it was connected to a chassis) and reconnected the FPGA VI reference bitfile to the new one. Did not do anything.
4. I had reboot the cRIO 9073 several times now. does not seem to do anything.
What could I have done wrong? and can anyone please help me?
I tried to revert it back to the old working rtexe but when I use the old one, the cRIO doesn't even connect to the IP address.
Thank you wholeheartedly and bless you who can fix this problem for this poor soul.
ps. I'm using LV 2015 and all other module versions are 2017.
Are you using a pure FPGA or scan engine / fpga hybrid? Anyways I find that after updating the software on a cRIO you usually want to redeploy the project settings through the project. Right click on the chassis icon in the project and hit "deploy all". It often helps to run the RT main VI in interactive mode to debug what is happening.
Thank you SO much for your reply. I really appreciate your insights!
I don't know if I am using a pure FPGA or scan enging.. is there a way to check?
Also, when you updated the software on a cRIO, did you have to format it? I had redeployed some of the vi, but had not done 'deploy all' so I tried as you suggested and it was not able to be completed. After fidgeting with it a bit, I retried but the deployment stopped with 'Waiting to connect to the target.' I attached what I see on the screen.
I was recommended to recompile all the FPGA vis, so I did and tried 'deploy all' again but the same thing happened.
Then, I checked the error log and I get tons of errors similar to this:
VI_BROKEN (0): [VI "NI_PID_pid.lvlibID (DBL).vi" (0x0100a530)]
VirtualInstrument:etOrClearBadVILibrary - now VI is bad on [VI "NI_PID_pid.lvlibID (DBL).vi" (0x0100a530)]
I attached the txt file which lists all the errors. Any idea or experience?
Thank you so much for your time!
ah yes. When the executable builds but the a bunch of broken VIs occur when you try to run it on the target. Perhaps you are missing software components that should be installed but aren't? For example network streams require you to install support for them. I have also seen broken executables caused by using user-defined IO variables in "absolute" reference mode as opposed to relative.
It's hard to tell which VI is the root of the problem from the error log in my experience. Does everything work when you run in interactive mode through the project?