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cRIO 9068 Strange behaviour after RT Exit

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I'm working with a 9068 and just ran into a strange issue where one while loop out of three on the FPGA appears to stop when the Main RT code exits. 

 

If I start the FPGA code interactively after the RT code has stopped, I can see the other two loops operating normally, and the stopped one showing a 0 Loop Period. 

 

On restart and reconnect of the RT and UI, the other two loops send data normally.  But the stopped loop will not send data again until the chassis has been reset. 

 

Oddly, if I trigger the System Restart.vi to reboot the chassis programmatically from the RT code when it shuts down, it only seems to actually restart the chassis every second launch, even though the code is being called each time.   Every second reconnect takes much longer and all loops are running. 

 

Also, if the FPGA panel is open and running interactively, all of the loops keep running.  Same if I don't close the reference to the FPGA when shutting down the RT code. 

 

Any thoughts on what could be happening? 

 

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Patrick Allen: FunctionalityUnlimited.ca
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When you say "running interactively", do you mean running it in simulation mode on your host PC?

 

Is there any conditional statements that your code may be missing that only triggers on startup? Or that stops the loop on a condition that is miss triggered?

 

Could you possibly post your code so that we can look at the start up functions and the loop that isn't operating properly?

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In this case I meant running the FPGA front panel in interactive mode.  The FPGA VI itself was "running" on the PC and I was viewing the front panel. 

 

I think I've isolated the issue to closing the FPGA reference.   

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Patrick Allen: FunctionalityUnlimited.ca
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Glad you figured it out! Let us know if we can help out with anything else.

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